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7. CIRCUIT DIAGRAM
1
2
3
A
B
ANT406
ANT405
1
R440
C463
NA
15p
C
C406
L407
2.2p
GND405
3.9nH
D
E
LBAND_PAM_IN
R413
HBAND_PAM_IN
0
R420
R421
R415
NA
NA
NA
F
G
H
1
2
3
LGE Internal Use Only
4
5
6
2V85_RF
C437
0.1u
SW401
KMS-506
GND11
26
C404
R406
GND10
25
G2
ANT
RF
ANT
GND9
G1
1
24
0
100p
GND8
23
GND7
11
C410
L410
0.5p
33nH
R454
0
L409
1nH
L408
15nH
GSM850
GSM900
DCS1800
PCS1900
2V85_RF
C445
C446
C443
C444
C441
C442
C439
C440
1.8p
1.8p
1.8p
1.8p
1.8p
1.8p
1.8p
1.8p
C416
0.1u
L404
L405
L402
L403
18nH
18nH
5.6nH
5.6nH
2V85_RF
1V5_RF
1V5_RF
2V85_RF
C417
C457
1u
10u
C418
C419
C420
0.1u
47n
0.1u
FE2
33
VBIAS
34
VDDTX1V5
VDDRX2V8
R412
35
20
TX1
VDDRX1V5
U402
0
36
19
R414
TX2
PMB6272
VCO_RC
37
18
820
VDDTX2V8
VDDVCO2V8
R418
38
17
R416
VDDMIX2V8
EN
39
16
NA
10
GND3
VDDXO2V8
40
15
C424
C425
FSYS1
14
0.1u
0.1u
GND4
GND1
41
13
2V7_VCXO
1V5_CORE
2V85_RF
R423
100p
R424
C426
10
0
C428
C429
C427
1000p
0.1u
0.1u
BT_CLK
R426
RF_CLK
0
R427
RF_DA
0
R428
QX
0
C432
C433
NA
NA
R429
Q
0
R430
IX
0
C434
C435
NA
NA
R431
I
0
4
5
6
7
8
9
R403
100
ANT_SW1
R405 100
ANT_SW2
R441
100
ANT_SW3
C454
C453
C452
100p
100p
100p
VSUPPLY
NC3
LB_RFIN
20
7
R407
NC2
U401
VRAMP
15
6
0
NC1
VMODE
RF3158
10
5
VBATT
4
LB_RFOUT
TX_EN
12
3
BAND_SEL
2
HB_RFOUT
HB_RFIN
18
1
L406
C401
C402
C409
C403
10nH
100p
100p
100p
100p
C408
C414
68u
27p
2V7_VCXO
R448
0
C421
C422
0.1u
0.1u
22K
R417
R419
RF_TEMP
RF_EN
0
10K
PT401
26MHZ_MCLK
C423
1000p
R449
0
X401
R425
1K
3
1
OUT
VCONT
AFC
4
2
VCC
GND
C430
C455
C431
NA
1500p
26MHz
1uF
Changed by:
mentor
7
8
9
- 122 -
10
11
LBAND_PAM_IN
PA_LEVEL
MODE
TXON_PA
PA_BAND
HBAND_PAM_IN
Engineer:
LG Electronics
Drawn by:
R&D CHK:
W.J.KIM
TITLE:
ME820
DOC CTRL CHK:
Issue 1.0
MFG ENGR CHK:
Date Changed:
Time Changed:
QA CHK:
REV:
Drawing Number:
2005-06-01
3:07:35 pm
10
11
Copyright © 2007 LG Electronics. Inc. All right reserved.
Only for training and service purposes
12
A
B
C
D
E
F
G
H
Size:
A3
12 1 8 A
Page:
3/5
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