S3.3. Analog Video Block Diagram - Panasonic DMR-BS750EG Service Manual

S3.3. Analog Video Block Diagram

AV IO P.C.B.
P59007 P3003 SD C OUT
19 32
P59007 P3003 SD Y OUT
17 34
FROM
P59007 P3003 HD PR OUT
DIGITAL P.C.B.
14 37
P59007 P3003 HD Y OUT
12 39
P59007 P3003 HD PB OUT
10 41
JK3901
21 PIN JACK
AV1 AV1 VIDEO
20
(TV)
AV3
VIDEO IN FRONT V IN
P6702 P58005 P58007 P3003
JK3801 2
1 21 30
FRONT JACK
1
JK3901
21 PIN JACK
AV2 R/C
RED/C 15
AV2 G
AV2 GREEN 11
(DECODER/EXT)
AV2 B
BLUE 7
AV2 V/Y
VIDEO/Y 20
IC3001
(VIDEO PROCESSOR)
6MHz
91 BIAS
BPF
+
6MHz
93 CLAMP
LPF
CLAMP/
95
BIAS
97 CLAMP
CLAMP/
99
BIAS
AV1 V
33 CLAMP
AV3 Y
41 CLAMP
AV3 C
45 BIAS
AV3 V
37 CLAMP
AV4 V
35 CLAMP
AV4 Y
39 CLAMP
AV4 C
43 BIAS
(SW10)
BIAS b
AV2 R/C
1 CLAMP a
AV2 G
3 CLAMP
AV2 B
5 CLAMP
AV2 V/Y
31 CLAMP
sc
P Y IN2
P Y OUT
14
P Y IN1
sa
P R IN1
P B OUT
11
sb
P B IN1
P R OUT
7
(SW1)
6MHz
a
12MHz b
c
(SW3)
AV1
a
R-C
b OUT
9
c
d
(SW4)
6MHz
a
12MHz b
c
AV1
B
OUT
12
(SW5)
AV1
6MHz
G
a
OUT
12MHz b 17
c
20
(SW17Y)
a (SW7)
Y
a OUT
19
b
(SW17C) b
a (SW8)
C
a
OUT
b 22
(SW17V) b
(SW9)
a
a
V
b OUT
23
b
24
SV1
a
AV1
b
V/Y/C
c
OUT
d 26
e
SV2
a AV2
V
b
OUT
c 28
d
e
C-ADC
AV1 V OUT
81
AV3 Y
AV3 C
V/Y
AV3 V
ADC
ADC
AV4 V
OUTPUT
OUT
AV4 Y SELECT 83
SWITCH
AV4 C
CIRCUIT
V SYNC
AV2 R/C
OUT
AV2 V/Y V-SYNC SEP 82
TUNER V
SCL
88
IIC BUS
LOGIC SDA
89
TUNER
V
CLAMP 30
S-9
:REC SIGNAL :PB SIGNAL
JK3001
6
PR
COMPONENT
7
VIDEO OUT
PB
8
PY
5
JK3901
21PIN JACK
15 RED/C
7 BLUE
AV1
(TV)
11 GREEN
19 VIDEO/Y
JK3001
VIDEO OUT
4
1
JK3901
21PIN JACK
AV2
19 VIDEO
(DECODER/EXT)
CPN CIN P3003 P58007
43 8
V/Y IN P3003 P58007
TO
44 7 DIGITAL P.C.B.
V SYNC P3003 P58007
24 27
P3003 P58007 IIC CLK
IC59501- 34 FROM/TO
7 44
TIMER
P3003 P58007 IIC DATA
SECTION
8 43 IC59501- 33
P3003 P58007
< RGB CPSV >
46 5
P3003 P58007
< G R IN A >
48 3
TO
P3003 P58007
DIGITAL P.C.B.
< G G IN A >
49 2
P3003 P58007
< G B IN A >
50 1
5V
2.3V
1.0V
DMR-BS750EG,BS850EG
Analog Video
Block Diagram
PROGRESSIVE/
INTERLACE
OUT