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19.9. Coprocessor Circuit
1
2
3
SCHEMATIC DIAGRAM - 19
A
K
COPROCESSOR CIRCUIT
B
C0CBCBC00140
C
CN1701
B
+5.3V
1
TO
DGND
2
MAIN CIRCUIT
IPHONE_CPREADY
3
(CN2014)
IPHONE_CPRESET
4
IN SCHEMATIC
IPHONE_I2C_SCL
5
DIAGRAM - 6
D
IPHONE_I2C_SDA
6
E
F
G
H
1
2
3
4
5
6
: +B SIGNAL LINE
5
4
IC1702
VOUT
NC
+3.3V REGULATOR
VIN
VSS
ON/OFF
1
2
3
R1702
4.7K
Q1702
B1CFGC000004
G
LEVEL SHIFTER
D
S
Q1704
B1CFGC000004
G
LEVEL SHIFTER
D
S
R1731
0
Q2003
B1GBCFLL0037
INVERTER
4
5
6
7
8
9
10
40
39
38
37 36
35
34
33
32
31
X1701
H0J327200099
1
NC
30
2
NC
29
XIN
3
XOUT
NC
28
[1] VCC
4
CLK_EN
[8] I2C_ADDR_0
NC
27
[9] I2C_ADDR_1
IC1701
5
NC
NC
26
[10] I2C_ADDR_2
MFI341S2095
6
NC
NC
25
[21] NC
IPOD VIDEO
I2C_SCL
[31] SYS_CLK_OUT
NC
7
24
8
NC
23
NC
9
22
10
21
11
12
13
14
15
16
17
18
19
20
7
8
9
10
115
SA-PT460EB / SA-PT460EG
11
12
13
SA-PT460EB/EG COPROCESSOR CIRCUIT
11
12
13
14
A
B
C
D
E
F
G
H
14
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