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5

PWROK MAP

D
C
VRM_GD
B
VRMPWRGD assertion to ICH8 occurs at
least 10ms prior to PWROK_3V assertion
to the ICH9.
A
5
4
Intel LGA775 Processor
H_PWRGD
Bearlake-Q
MCH_CLPWROK
ICH_SYNC#
ICH9
CK_PWRGD
Front Panel
PWRBTN
4
3
VTT_PWG
VTT_PWRGOOD signal must be
delayed 1-10ms after
VTT_FSB for proper
clock/cpu function
PWRGD
SLP_S4#/SLP_M#
SLP_S3#
CK505
IT8718F
PS_ON#
3
2
VRM 11
Intersil 6312
VRM_EN
3-Phases PWM
VID_GD#
MS7
VRM_GD
PWR_OK
POWER CONN
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
MICRO-START INT'L CO.,LTD.
Title
Title
Title
PWROK MAP
PWROK MAP
PWROK MAP
Size
Size
Size
Document Number
Document Number
Document Number
Custom
Custom
Custom
MS-7377 (BELEM) uBTX
MS-7377 (BELEM) uBTX
MS-7377 (BELEM) uBTX
Date:
Date:
Date:
Friday, August 17, 2007
Friday, August 17, 2007
Friday, August 17, 2007
2
1
D
C
B
A
Rev
Rev
Rev
10
10
10
Sheet
Sheet
Sheet
32
32
32
of
of
of
35
35
35
1

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