Pacific 3 (T6Tf4Hfg); Pacific 3 Cmos + Lvds Interface; Pacific 3 Control (Diagram B06C) - Philips 32PFL9432/98 Service Manual

EN 182 9. Q528.1A LA
9.8.6

PACIFIC 3 (T6TF4HFG)

The PACIFIC 3 performs the following tasks:
• Colour processing.
• Sharpness improvement.
• Backlight dimming.
• AmbiLight.
• Display (LVDS) switch on/off.
• Pattern generator.
A configuration flash memory is added (item 7GE1).
Configuration
Flash memory
Circuit Descriptions, Abbreviation List, and IC Data Sheets
Single LVDS - in ( PNX85xx)
Double LVDS in ( FPGA)
Figure 9-23 PACIFIC 3 CMOS + LVDS interface
Resonator 60MHz
From
PNX5050
CMOS input :Vsync
LCD-Power -ON
I2C SSB
Figure 9-24 PACIFIC 3 control (diagram B06C)
The PACIFIC 3 interfaces:
• Video input:
– EU sets: CMOS from PNX5050
• Video output: LVDS (single or dual) to display or DFI panel.
• Backlight dimming: pulse-width modulated (PWM) followed
2
by PWM to I C conversion.
• AmbiLight: pulse-width modulated (PWM) followed by
microprocessor.
Refer to figure "PACIFIC 3 CMOS + LVDS interface" for details.
PWM ambi
to µP
Single or double
LVDS -out to display
H_16770_137a.eps
240707
RESET from PNX85xx
Vsync to Scanning
Back Light D isplay
To dimming circuit
H_16770_138.eps
130707