Acer B223W Service Manual page 27

c. Input signal timing
Support Input Timing Table
The input signal timing specifications are shown as the following table and timing diagram.
Signal Item
Clock
Dclk
T
V_TOTAL
T
V_DATA
Vertical
T
Horizontal T
H_TOTAL
T
H_DATA
T
Note:
Because this module is operated by DE only mode, Hsync and Vsync input signals should be set
to low logic level or ground. Otherwise, this module would operate abnormally.
DE
DCLK
DE
DATA
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TO ANY OTHER FORMS WITHOUT PRIOR WRITTEN PERMISSION FROM INNOLUX DISPLAY CORPORATION.
Description
period
frequency
V total line number
Data duration
V-blank
VB
f frequency
V
H total pixel number
Data duration
H-blank
HB
INPUT SIGNAL TIMING DIAGRAM
Tvd
Tc
Thb
SPEC NO.
PAG E
Min. Typ.
12.2 16.8
56 59.6
1059 1080
1050 1050
9
56
890
840
73
Tv
Tvb
Th
Thd
M T 2 2 0W W 0 1 V. 0
12/23
Max.
17.9
82
1100
1050
30 50
60 76
920 1004
840 840
80 164
Unit
nS
MHz
T
H
T
H
T
H
Hz
DClk
DClk
DClk