Camera And Y/C System Block Diagram - JVC GR-FX15EK Service Manual

CAMERA AND Y/C SYSTEM BLOCK DIAGRAM (1/2)

0 2 CCD
5
IC5301
Q5301
CN5301
7
BUF
OP BLOCK
13
14
1
CCD
2
IMAGE
SENSOR 3
4
10
CN5301
3 9 10 11 12 1314
4
12 6 5 4 3 2 1
CN22
3
CN15
F_SENS 7
23
Z_SENS
IC4501(F/Z/I/MDA)
26
FOCUS3 16 BRIDGE
24
18 DRIVER
FOCUS1
28
FOCUS4 17 BRIDGE
2
30
DRIVER
FOCUS2 19
10
4
ZOOM2 BRIDGE
12
DRIVER
ZOOM4 2
14
ZOOM3 1
BRIDGE
16
DRIVER
ZOOM1 3
HE_IN+ 13
HE_OUT- 9
HE_IN-
10
HE_OUT+ 12
DUMP- 6
DRIVE+ 14
DUMP+
5
1
JIG_CONN.
CN25
RXD
RXD 8
TXD
TXD 7
A
0 1 MAIN
C
IC5201
(TG/CDS)
44
(CDS/AGC/AD/TG)
C
CN22
CCD_OUT 51 CDSIN
5 10
A/D
CDS PGA
54 BLKSH
CONV
T. G
53 BLKFB
DC
OFFSET
SERIAL INTERFACE
22 26 30 31 32 33 34 35 38
7 9 14 12 8 13 10
18
OV4
17
OV3
3
OV2 (V_DRIVER)
5
OV1
1
OSUB
CCD-HV
D5201
OSCIN 36
TO DSP
32
VD
VDVHS
SCLK 35
SERIAL-
SDATA 34
PULSE
PARARELLE
GENERATOR
DECODER
33
LATCH
38
RESET
REG 4.8V
IC4201
R4262
Q4251
+ 6
AMP
C4256
WHITE
( )
BALANCE
SENSOR
B C
IC4001(DSP)
(DSP)
AD9
D9 12
D8 11 AD8
D7 10 AD7
100
AD6
D6 9
AD9 AD9
D5 8 AD5
OB
D4 7 AD4
CLAMP
AD3
D3 6
AD0
AD0
D2 5 AD2 110
D1 4 AD1
AD0
D0 3
CDS_CLK
ADCLK 39 137
AD1_CK
15 TG_CLK 118
CAMCK
132
CLKI
138
TL5201
CAMADCK
HD 16 113
HDTG
VD 17 114
VDTG
STROB/Vgate 41 99
LHFO
ID 1 112
ID
MONI 60 38
PBLK
CS 62 134
CLKCPU
63 S03
Sdata
SCK 64 SCK3
V_DSP_CS
V_PULSE
169
CLKOUT
35
CDS_CS AD0
AD1
AD2
36
TL5202 CCD_CS AD3
21
TL5203 DSGAT AD4
AD5
IC5202(TG/CDS)
AD6
AD7
AD8
AD9
AD10
AD11
AD12
IC101(CPU) AD13
AD14
AD15
REG_3.2V
R/W(L)
6
RST
ASTB
C5226
DSTB(L)
123
FOCUS_SENS
124 OMT
ZOOM_SENS
WAIT(L)
V_FF
LENS_CLK 26
LENS_MDA_CLK
VDVHS
FRP
10
SCK3
9
SO3
LENS_CS
41
LENS_MDA_CS
4
DSP_RST
IC4201,IC4202
(F/Z/I/MDA)
OSD_CLK
OSD_CS
OSD_DATA
DSP_RST
16
HALL IRIS_O/C
125
AMP
HOLE
R4209,C4206
59
+ LPF
IRIS_PWM
MOTOR
- +
DRIVE
TXD
AMP
(COMP)
RXD
RXD
8 12
IR_FLICK
121
IR_DC
D E
2-28
V/H
APT
CTL
G
γ
PROCESS
CTL
IH
DL
Y/C
γ
SEPA WB
(3LINE)
IH
RGB G
MATRIX
DL SEPA CTL
γ
126 STD
124
SDCK
DATA
SET
34
125 SLD
79 117
ADDV
116
HDMASK
145 7 BUS0
AD0
146 8
147 9
84
148
11
149 12
150 13
151
14
152 16
155 17
156 18
157 20
IC4002
158 21
(DSP)
159 22 42
160 23
161 24
162 25 BUS15
AD15
140 5 RW
R/W_L R/W_L
142 6 ASTB
ASTB ASTB
141 1 DSTB
DSTB_L DSTB_L
98 35 OMT
OMT
OMT
36
170 BUSY
WAIT_L WAIT_L
73 129 SW30
V_FF V_FF
110 240 VREF0
VDVHS
VDVHS
104 31 FRP
CFM CFM
15 28 HDCPU
HD HD_H HD_H
96 29 VDCPU
VD_H
VD VD_H
103 30 FLDCPU
FI FI FI
25 OSD_CLK
31 OSD_CS
24
OSD_DATA
4 DSP_REST DSP_REST 140
CLR
71
X1
X101
MAIN SYSTEM
70 CLOCK (16MHz)
X2
3 TXD
193 BLK_1
BLK1
194 BLK_2
BLK2
VBLK
195
94 RXD
VBLK
192
VB
191
2 RXD
VG
188
VR
186 VC_1
VC1
187 VC_2
VC2
CLKOSD
185
CLKOSD
F
C
V_PB_C
a
DSP CONTROL
INTER FACE
C Y C Y
87 73 81 92 96 91 67 72 59 66 88 97 90 95
39 7 43 32 34 37 38 42 39 7 43 8 10 9 13
C Y C Y
(MEMORY)
WRITE BUFFER DOUT BUFFER
WRITE RESISTOR READ RESISTOR
MEMORY CELL ARRAY
IC4003(DSP)
(OSD)
11
BLK1
13
BLK2
15
VBLK
VB 18
VB
VG 17
VG
DSP_REST
VR 16 4
VR PCL
12 3 OSD_DATA
VC1 DATA
14 2 OSD_CS
VC2
CS
OSD_CLK
8 1
OSCIN CLK
G