Monitor System Block Diagram - JVC GR-FX15EK Service Manual

MONITOR SYSTEM BLOCK DIAGRAM

FROM REG
CN16 CN7601
REG_4.8V
REG_4.8V 5 20
REG_4.8V
6 21
FROM CPU
LCD_CTL
LCD_CTL 4 22
FROM CPU
DSP_REST
DSP_REST
18 8
PMIRROR
PMIRROR 19 7
FROM DSP
HDCVF
HDCVF 15 11
VDCVF
VDCVF 16 10
FROM CPU
RVS_SW
REV_SW 25 1
HRP1
HRP1 17 9
TO DSP
FROM DSP
ROUT
GOUT
BOUT
0 1 MAIN
T7501 T7501
2 6
F7501 F7501
3
4
CFL
Q7503 Q7503 Q7501 Q7501
10
Q7504 Q7504 Q7502 Q7502
1
CTL CTL OSC OSC
REG_3.2V
IC7602
R7607
L7605 5
7
6
C7617
R7612
36 34 33 31 30 29 28 27
37
VCO
38
39 RESET
40
COUNTER V.SYNC
MODE SEL
IC7601
PHASE
COMP
QVD POL
EQ
SEL CTL
PULSE
CANCEL
48
1 2 3 4 5 6 7 8
NC NC NC NC
SW Q7605 SW Q7607
Q7001
BUF&SW
LCD (DAC_3.2V)
Q7003
BUF&SW
CVF
CLK1
RL
CLK2
STV2
CLK3
26 25
D7604
STH2 24 STH2
STH1 23 STH1
22 Q2H
QH
IC7603
H.SYNC
21 2 4 OEH
OEH
STV1 20 STV1
18
OEV2 OEV
FIELD
17
DET
NC
CPV 16 CPV
ZOOM
CORRECT
REG_15V
INT/EXT 15
IC7602
R7604
C7609
POL 14 2
- 1
-
UD 13
3
R7601,R7602 +
+
LT R7605
12 Q7606
SW
R
G
B
CN7601
16 14 12
10 12 14
CN16
Q7002
BUF&SW
Q7003
BUF&SW
CVF_G
Q7001
CVF_R
BUF&SW
Q7005
CVF_B
BUF&SW
LCD MONITOR
0 7 MONITOR
CN7602
L7604
VGH
REG_15V 9 9
L7601 VDD
8 8
REG_3.2V
VEE
MREG_4.8V 11 11
VSS
2 2
VSS(REG_-15V)
CLK1
21 21
RL
13 13
CLK2
20 20
STV2
7 7
CLK3
19 19
STH2
12
12
STH1
24 24
Q2H
22 22 LCD MODULE
OEH
23 23
STV1
3 3
OEV
6 6
CPV
5 5
REG_3.2V
R7645
C7622
VCOM
10 10
R7646
Q7601-Q7604
VGL
AMP 1
1
UD
4 4
R
15 15
G
16 16
B
17 17
0 6 C-VF BL
TO BW/CVF
CN11
VF_BLK
VF_BLK 20 6
5
REG_4.8V
REG_4.8V 19 3
2
1
0 6 C-VF
FROM LCD/CVF CN7701
VF_COM
VF_COM 18 18
CVF_G
17
17
CVF_R
16
16
CVF_B
15 15
REG+12V
14 14
REG+12V
REG_3.2V
REG_3.2V 13 13
HDCVF
HDCVF 9 9
FROM/TO
VDCVF
8 8
VDCVF
DSP HRP2
HRP2 7 7
CVF_CS
CVD_CS 5 5
CVF_SCK3
FROM BW/CVF CVF_SCK3 4 4
CVF_SO3
CVF_SO3 3 3
SI3
FROM CPU SI3 2 2
BWYGAIN
FROM DSP 1 1
BWYGAIN
OPEN
CN7702
COM
16
GREEN
15
RED
14
BULE
13
HCK1
11
HCK2
10
HST LCD
9
RGT MODULE
8
DWN
7
EN
6
STB
5
VCK
4
VST
3
VDD
1
2-27