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CAMERA AND Y/C SYSTEM BLOCK DIAGRAM (1/2)
0 2 CCD
IC5301
Q5301
CN5301
7
CCD_OUT
BUF
5
OP BLOCK
13
14
1
CCD
2
IMAGE
SENSOR
3
4
10
CN5301
3 9 10 11 12 1314
12 6 5 4 3 2 1
CN22
CCD-HV
CN15
F_SENS
7
Z_SENS
23
IC4501(F/Z/I/MDA)
26
FOCUS3
16
BRIDGE
24
DRIVER
FOCUS1
18
28
FOCUS4
17
BRIDGE
30
DRIVER
FOCUS2
19
PULSE
GENERATOR
10
ZOOM2
4
BRIDGE
12
DRIVER
ZOOM4
2
14
ZOOM3
1
BRIDGE
16
ZOOM1
3
DRIVER
HE_IN+
13
HE_OUT-
9
HE_IN-
10
HE_OUT+
12
DUMP- 6
DRIVE+
14
DUMP+
5
JIG_CONN.
CN25
RXD
RXD
8
TXD
7
TXD
0 1
MAIN
C
IC5201
(TG/CDS)
44
(CDS/AGC/AD/TG)
C
CN22
51
CDSIN
10
A/D
54
BLKSH
CDS
PGA
CONV
T. G
53
BLKFB
DC
OFFSET
SERIAL INTERFACE
STROB/Vgate
22
26
30
31
32
33
34
35
38
IC5202(TG/CDS)
7
9
14
12
8
13
10
18
OV4
17
OV3
3
OV2
(V_DRIVER)
5
OV1
1
OSUB
D5201
OSCIN
36
TO DSP
32
VD
VDVHS
SCLK
35
SERIAL-
SDATA
34
PARARELLE
DECODER
LATCH
33
38
RESET
IC4201,IC4202
(F/Z/I/MDA)
HALL
AMP
MOTOR
DRIVE
AMP
REG 4.8V
IC4201
R4262
Q4251
+
6
8
AMP
C4256
(
WHITE
)
BALANCE
SENSOR
IC4001(DSP)
(DSP)
D9
12
AD9
D8
11
AD8
AD7
D7
10
100
D6
AD6
9
AD9
AD9
D5
8
AD5
OB
D4
7
AD4
CLAMP
D3
6
AD3
AD0
AD0
IH
AD2
D2
5
110
DL
AD1
D1
4
D0
3
AD0
IH
CDS_CLK
137
ADCLK
39
DL
AD1_CK
TG_CLK
118
15
CAMCK
132
CLKI
138
TL5201
CAMADCK
HD
16
113
HDTG
VD
17
114
VDTG
41
99
LHFO
ID
1
112
ID
MONI
60
38
PBLK
CS
62
134
CLKCPU
63
S03
Sdata
SCK
64
SCK3
34
V_DSP_CS
79
V_PULSE
169
CLKOUT
35
145
CDS_CS
AD0
146
AD1
147
AD2
36
148
TL5202
CCD_CS
AD3
149
21
TL5203
DSGAT
AD4
150
AD5
151
AD6
152
AD7
155
AD8
156
AD9
157
AD10
158
AD11
159
AD12
160
IC101(CPU)
AD13
161
AD14
162
AD15
REG_3.2V
140
R/W(L)
6
RST
142
ASTB
C5226
141
DSTB(L)
123
FOCUS_SENS
98
OMT
124
ZOOM_SENS
170
WAIT(L)
73
V_FF
LENS_CLK
26
LENS_MDA_CLK
110
VDVHS
104
FRP
10
SCK3
15
HD
9
SO3
96
VD
LENS_CS
41
LENS_MDA_CS
103
FI
4
DSP_RST
25
OSD_CLK
OSD_CLK
31
OSD_CS
OSD_CS
24
OSD_DATA
OSD_DATA
4
DSP_REST
DSP_RST
16
IRIS_O/C
125
71
X1
HOLE
R4209,C4206
70
59
+
LPF
IRIS_PWM
X2
-
+
3
TXD
TXD
(COMP)
RXD
94
RXD
2
RXD
RXD
12
IR_FLICK
121
IR_DC
2-53
2-54
V/H
APT
CTL
γ
G
PROCESS
CTL
Y/C
γ
SEPA
WB
(3LINE)
RGB
G
MATRIX
SEPA
CTL
γ
126
STD
124
SDCK
DATA
SET
C
Y
125
SLD
117
ADDV
116
HDMASK
7
BUS0
AD0
8
9
84
87 73
11
12
13
14
16
17
18
20
IC4002
21
(DSP)
22
42
39
7
23
24
25
BUS15
AD15
C
Y
5
RW
R/W_L
R/W_L
6
ASTB
ASTB
ASTB
1
DSTB
DSTB_L
DSTB_L
35
OMT
OMT
OMT
36
BUSY
WAIT_L
WAIT_L
WRITE BUFFER
129
SW30
V_FF
V_FF
240
VREF0
VDVHS
VDVHS
31
FRP
CFM
CFM
WRITE RESISTOR
28
HDCPU
HD_H
HD_H
29
VDCPU
VD_H
VD_H
FLDCPU
30
FI
FI
DSP_REST
140
CLR
X101
MAIN SYSTEM
CLOCK (16MHz)
193
BLK_1
11
BLK1
194
BLK_2
13
BLK2
195
VBLK
15
VBLK
192
VB
18
VB
191
VG
17
VG
188
VR
16
VR
186
VC_1
12
VC1
187
VC_2
14
VC2
185
CLKOSD
CLKOSD
C
V_PB_C
a
DSP CONTROL
INTER FACE
C
Y
81
92 96 91
67
72
59
66
88 97 90
95
43
32
34
37 38
42
39
7
43
8 10
9
13
C
Y
(MEMORY)
DOUT BUFFER
READ RESISTOR
MEMORY CELL ARRAY
IC4003(DSP)
(OSD)
BLK1
BLK2
VBLK
VB
VG
4
DSP_REST
VR
PCL
3
OSD_DATA
VC1
DATA
2
OSD_CS
VC2
CS
OSD_CLK
8
1
OSCIN
CLK
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