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EN 132
9.
EM5A P/M
9.12 Horizontal (Line) Deflection (Diagram A3)
9.12.1 Principle
T ON
T OFF
T7421 conducting
3406
2492
LINEDRIVE 1
(HOP)
6406
EW_DRIVE
(HOP)
The HOP (located on the SSB) generates the line-drive pulses
(LINEDRIVE1), which have a frequency of 31250 Hz (T = 32 s)
for 50 Hz signals and 31468 Hz (T=31,77 µs) for 60 Hz signals.
When the LINEDRIVE1 signal is high, TS7409 and TS7408 will
conduct. A constant DC voltage will be applied across L5410,
causing a linear increasing current through this coil. The
secondary voltage of L5410 has a negative polarity so that
TS7421 will block.
When the set is switched "on", the current through L5410 is
supplied by the 5V2 Standby supply (via D6407), and taken
over by the +11D voltage (via D6408) of the main supply.
When the LINEDRIVE1 signal becomes low, TS7409 and
TS7408 will block. The voltage polarity across the primary
winding of L5410 will invert. The positive voltage on the
secondary winding will now drive TS7421 into conductivity.
Because of the storage time of the line transistor (TS7421),
L5410 cannot transfer its energy immediately to the secondary
side. This may result in high voltage peaks on the collector of
TS7409 and TS7408. To prevent that these peaks will damage
the transistors, a "snubber" circuit (C2414, C2412 and R3411)
will suppress them.
When the LINEDRIVE1 signal is high again, the above
described sequence starts again. Circuit L5411 and R3409 will
increase the switch "off" time of the line transistor.
Circuit Descriptions and Abbreviation List
COLD
6408
MAIN SUPPLY +11D
STANDBY SUPPLY +5V2
6407
3416
3411
2412
2414
7409
3414
7408
2415
3407
3404
3486
3412
1
7450-B
3
5
8
6
4
6615
2
3487
Figure 9-23 Line deflection circuitry
HOT
3409
5410
5411
2417
3417
141V
3488
+8VS
3418
3492
+8VB
3484
3481
7486
7487
3490
1
5
3483
7482
2
4
The line stage is started via a "slow start" principle. During start-
up, the HOP generates line drive pulses with a small T
a high frequency (50 kHz). T
gradually increased until the frequency is normal (31250 Hz/
31468 Hz).
The time interval from start to normal condition takes about 150
ms.
When switching off, the same procedure is followed, but now in
reverse order.
9.12.2 Implementation
To explain the operation of the line output stage, we use the
following start conditions:
•
C2433 is charged to max. 141 V (V
•
TS7421 is driven into conductivity.
5430
141V
7421
2420
Linearity Correction
*1
141V
5
S-correction
*2
5430
Y
X
X
X > Y
1
Deflection centre
7421
2420
2425
6423
2421
4
3
6480
2426
6422
7480
ARC
PROT
3479
CL 26532041_077.eps
is constant and T
OFF
5430
I Defl
141V
t1
t2
100V
Line defl.
6423
2425
+
7421
2433
141V
2421
-
41V
6422
2426
41V
5422
Figure 9-24 Line deflection part 1
Caused by
serial losses in
the line output stage
LINE
1417
1
DEFL. COIL.
2
2430
LINEARITY
3431
COIL.
(*1)
5421
2431
(*2)
2433
2
5422
1
170402
and
ON
is
ON
)
BAT
I
Defl
t2 t3
Line defl.
6423
2425
2433
2421
2420
6422
2426
5422
CL 96532156_024.eps
060199
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