Casio CTK-750 Service Manual page 8

Initial reset
When batteries are set or an AC adapter is connected, the reset IC provides a low pulse to the CPU.
The CPU then initializes its internal circuit and clears data in the working strage RAM.
Power ON reset
When the power switch is pressed, the CPU receives a low pulse of POWER signal. The CPU first raises
APO signal to +5V to generat DVDD voltage, then raises RESET signal to +5V. During this period the
gate array, the DSP and the key touch LSI initializes their internal circuit.
CPU (HD6433298A18P)
The 16-bit CPU contains a 32k-bit ROM, a 1k-bit RAM, seven 8-bit I/O ports, an A/D convertor and serial
interfaces. The CPU accesses to the working strage RAM, the DSP and the key touch LSI. The CPU also
controls buttons, LEDs, bender input and MIDI input/output.
Pin No. Terminal In/Out
1 P40
2 P41
3 P42
4 P43
5 P44
6 P45
7 P46
8 P47
9 TXD
10 RXD
11 P52
12 -RESET
13 -NMI
14 VCC
15 -STBY
16 VSS
17 XTAL
18 EXTAL
19, 20 MD1, MD0
21 AVSS
22 AN0
23 ~ 29 P71 ~ P77
30 AVCC
31 ~ 38 P60 ~ P67
39 VCC
40 ~ 56 P27 ~ P10
48 VSS
57 ~ 64 P30 ~ P37 Ijn/Out
Out KO signal data output
Out Clock for KO signal data
Out APO (Auto Power Off) signal output. ON: High, OFF: Low
Out Read enable signal output
Out Write enable signal output
Not used.
Out 10MHz clock output
In Wait signal input. Connected to +5V.
Out MIDI signal output
In MIDI signal input
Out Reset signal output
In Reset signal input
In Power ON signal input.
In +5V source
In Standby signal input. Connected to +5V.
In Ground (0V) source
In 20MHz clock input
In 20MHz clock input
In Mode selection input. (Internal ROM mode --- MD1: Hight, MD0: Low)
In Ground (0V) source for internal DAC
In Analog input. Connected to the bender volume.
In Button input signal input
In +5V source for internal DAC
Out LED segment signal output
In +5V source
Out Address bus
In Ground (0V) source
Data bus
Function
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