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Pin No.
Terminal
93
VCC5
94, 95
97 ~ 105
EA0 ~ EA14
107,109
110, 112
96
EWEB
106
EOEB
108
VCC7
111
ECEB
113 ~ 117
118
VCC4
119
GND4
120 ~ 122
123 ~ 130
ED0 ~ ED7
131
GND5
132 ~ 134
135, 136
Block diagram of DSP and DAC circuit
D0 ~ D7
A0 ~ A3
LSIS
RDAPO
WRAPO
RESET
16.384MHz
In/Out
In
+5V source
Out
Address bus for the effect RAM
Out
Write enable signal output for the effect RAM
Out
Read enable signal output for the effect RAM
In
+5V source
Out
Chip select signal output for the effect RAM
Not used.
In
+5V source
In
Ground (0V) source
Not sued.
In/Out
Data bus for the effect RAM
In
Ground (0V) source
Not used. Connected to ground.
Not used.
Sound Source ROM
TC5316200CP-C081
CE
A0 ~ A19
D0 ~ D15
RD0 ~
RA0 ~
RA22
RD15
RA19
DSP
HG51A115A01FD
ECEB EOEB EWEB
WE
OE
CS
PG
Effect RAM (256K-bit)
HM65256BLP
Function
SOLP: Sound data
BOK: Bit clock
WOK1: Word clock
SOLP
BOK
WOK1
EA0 ~
ED0 ~
ED15
EA14
D0 ~ D15
A0 ~ A14
— 9 —
DAC
ROUT
SI
CLK
LOUT
LRCK
UPD6376CX
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