Onkyo HTR-550 Service Manual page 64

IC BLOCK DIAGRAMS AND TERMINAL DESCRIPTIONS-17
Q8003 : AD8196 (HDMI/DVI Switch with Equalization)-1/2
BLOCK DIAGRAM
I2C_SDA
I2C_SCL
I2C_ADDR
VTTI
IP_A[3:0]
IN_A[3:0]
IP_B[3:0]
IN_B[3:0]
VTTI
AUX_A[3:0]
AUX_B[3:0]
PIN LAYOUT
I2C_ADDR
SERIAL INTERFACE
CONFIG
INTERFACE
+
4
4
–
+
4 EQ
4
–
HIGH SPEED
4
4
LOW SPEED
BIDIRECTIONAL
AVCC 1
IN_A0 2
IP_A0 3
AVEE 4
IN_A1 5
IP_A1 6
AD8196
VTTI 7
TOP VIEW
IN_A2 8
(Not to Scale)
IP_A2 9
AVCC 10
IN_A3 11
IP_A3 12
AVEE 13
14
RESET
AD8196
CONTROL
LOGIC
4
SWITCH
CORE
PE
4
BUFFERED
4
SWITCH
CORE
UNBUFFRED
42 AVCC
41 IP_B3
40 IN_B3
39 AVEE
38 IP_B2
37 IN_B2
36 VTTI
35 IP_B1
34 IN_B1
33 AVCC
32 IP_B0
31 IN_B0
30 AVEE
29 I2C_SDA
TX-SR505/505E
AVCC
DVCC
AMUXVCC
AVEE
DVEE
VTTO
+
OP[3:0]
ON[3:0]
–
AUX_COM[3:0]