Pioneer dvr-3100-s Service Manual page 113

5
UPD72852AGB-8EU (MAIN ASSY : IC5101)
QQ
3 7 63 1515 0
• IEEE1394 Physical IC
Pin Arrangement
Block Diagram
TE
L 13942296513
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.
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6
DGND 1
SCLK 2
IC (DL) 3
DV 4
DD
CTL0 5
CTL1 6
DGND 7
D0 8
D1 9
DV 10
DD
D2 11
D3 12
DGND 13
D4 14
D5 15
DGND 16
30
CMC
26
PC0
PC1 27
PC2 28
19
SUS/RES
LREQ 63
LPS 59
DIRECT 50
2
SCLK
58
LKON
5
CTL0
6
CTL1
Link
8 Interface
D0
I/O
9
D1
11
D2
D3 12
D4 14
D5 15
D6 17
D7 18
RESETB 55
Cable
x ao u163
Power
CPS 32
y
Status
i
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2 9
8
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q Q
3 6 7 1 3 1 5
Cable
Port 0
Arbitration
and
Control State
Machine
Logic
Cable
Port 1
Receive Data Voltage
Decoder and
and Current
Retimer Generator
Transmit Data Crystal Oscillator
Encoder PLL System
and
co
Transmit Clock
Generator
.
DVR-3100-S
7
9 4 2 8
TpBias1
AV
DD
TpA1p
TpA1n
TpB1p
TpB1n
AGND
TpBias0
AV
DD
TpA0p
TpA0n
TpB0p
TpB0n
AGND
RI1
AGND
0 5 8 2 9 9 4 2 8
39 TpA0p
38 TpA0n
TpB0p
37
TpB0n
36
46 TpA1p
45 TpA1n
44 TpB1p
43 TpB1n
41 TpBias0
48 TpBias1
34 RI1
m
23 XI
22 XO
8
9 9
A
B
C
9 9
D
E
F
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