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EN 148
9.
BJ3.0E PA
CAM Stand-by Mode
•
CAM stack still alive:
–
Active Front-End.
–
Active VIPER, Stby-uP.
•
Allows the CAM to request services:
–
Listen to OOB.
–
Firmware upgrade.
Connector
•
Mechanical
–
68 pins PCMCIA connector.
–
Voltage keying (LV type).
–
Type I, II, III.
•
Hot plug ability
–
Initial, V
is applied to the socket.
CC
–
Card detection (CD1 & CD2 = low).
–
Voltage sense pins (VS1 & VS2).
–
Power controller to set V
•
CIS structure
–
All PCMCIA cards have a CIS structure.
–
Information about size, speed, functions, ...
–
Distinguish between PC-card and CAM module
with inserted smart card.
–
Before reading the CIS, the PCMCIA driver is in an 8-
bit memory card mode with reduced address- and
control lines (only purpose is to read the CIS).
–
After reading the CIS, there is a personality change
and the driver is ready to communicate with a Cable-
card.
–
Once a card's client driver successfully parses the CIS
and obtains the system resources required by the card,
it assigns the resources to the card via the COR
(Configuration Option Register).
MPEG-2
TRANSPORT
STREAM
POD
INTERFACE
LOGIC
OUT OF BAND
SERIAL DATA
COMMAND
INTERFACE
PCMCIA
CONNECTOR
Figure 9-9 Example of CAM (POD) design
9.4.3
Communication Channels
In Band (IB)
•
PAL - DVB-COFDM 2K/8K analog channels:
–
8-VSB modulation (3 bits/symbol).
–
51 - 858 MHz (UHF and VHF).
–
6, 7 or 8 MHz bandwidth.
–
Not via CAM, but via MPIF.
–
With VBI (Vertical Blanking Interval) signals for closed
captioning.
9.5
MPIF (PNX 3000)
For a (more) detailed description of the Multi Platform
InterFace (MPIF; PNX 3000) converters see the BP2.xU
manual.
Circuit Descriptions, Abbreviation List, and IC Data Sheets
and V
.
CC
PP
COPY
MPEG-2
PROTECTION
TRANSPORT
ENGINE
DEMULTIPLEXER
AND
PAYLOAD
REMULTIPLEXER
DECRYPTION
ENGINE
SECURE
OUT OF BAND
uP
CPU
PROCESSING
MEMORY CONTROLLER
FLASH
RAM
POD MODULE
F_15400_075.eps
9.6
PNX2015
The functional blocks of the PNX2015 are:
•
Audio Video Input Processor (AVIP).
•
3D Comb Filter (COLUMBUS).
•
High Definition MPEG Decoder (HD Subsystem).
•
LVDS transmitter.
•
Stand-by Processor for low-power control.
For a (more) detailed description of the PNX2015 see the
BP2.xU manual.
9.7
VIPER 2 (PNX 8550)
9.7.1
Introduction
The PNX8550 is a highly integrated media processor intended
for deployment in analog, digital, and hybrid TV receivers. It
can be used for 100 Hz interlaced as well as 60 Hz progressive
screens. It is fully capable of performing advanced video
improvement algorithms, such as Digital Natural Motion™, on
Standard Definition analog or digital sources. It includes an HD
capable de-interlacer for converting interlaced HD
transmission signals to progressive output for driving wide-
XGA class Plasma or LCD displays. Two 32-bit 240 MHz VLIW
media processors, referred to as the TriMedia TM3260 CPU
core, carry out the advanced video improvement processing as
well as all audio operations. Fixed hardware functions perform
stable core video functions, such as picture level MPEG2
decoding, scaling, image composition and pixel post
processing.
The PNX8550 provides a primary digital (YUV or RGB) output
to connect to the display specific output processor. In addition,
a secondary analog video output (CVBS or S-Video) for a VCR
is available. This is the so-called DENC-out. It can operate
either in analog PAL/NTSC or digital mode.
For a (more) detailed description of the PNX8550 see the
BP2.xU manual.
9.8
PACIFIC 3
A new IC, called Pacific 3, provides Pixel Plus in all models.
100505
This ensures additional sharpening, and contrast and colour
enhancements to the picture.
9.9
Ambient Light
For a (more) detailed description of the Ambient Light module
see the BP2.xU manual.
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