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Circuit Diagrams and PWB Layouts
SSB v2: Digital Channel Decoder
8
7
DIGITAL CHANNEL DECODER
B04
FAT_IN-
F
FAT_IN+
E
D
R536
33R
1
8
TS0INDATA7
TS0INDATA6
2
7
3
6
TS0INDATA5
4
5
TS0INDATA4
C
TS0INDATA3
TS0INDATA2
TS0INDATA1
TS0INDATA0
TS0INVALID
TS0INSYNC
TS0INCLK
B
A
8
7
TCM2.0E LA
7.
6
5
C513
C568
1000P
NC/20P
C514
C569
1000P
NC/20P
R508
U502
XTALO
1
36
AVSS33_3
RF_AGC
2
35
AVSS33_2
IF_AGC
XTALI
3
34
XTALI
VDD3.3_3
4
33
XTALO
GPIO0
AVDD33
5
32
AVDD33_2
/RESET
6
31
ALC_IN
XTAL_SEL1
DVDD12
7
30
VDD1.2
XTAL_SEL0
8
29
DGND1.2
DGND3.3_1
9
28
TSDATA7
VDD3.3_2
10
27
TSDATA6
VDD1.2_2
11
26
TSDATA5
HOST_SDA
DVDD33
12
25
VDD3.3
HOST_SCL
MT5133
R535
33R
8
1
2
7
3
6
4
5
33R
R542
33R
R543
33R
R544
L510
33R
R545
120R
6
5
51
4
3
DV33
DV33
0R
TUNER_SCL0
AV12
TUNER_SDA0
R507
0R
DV33
R150
NC/1K
MT5133-GPIO-AD
R506
1K
MT5131_IF_AGC
IF_AGC
CLOSE TO MT5133
DVDD33
C509
0.047U
R505
100R
MT5133_RESET
R504 10K
DVDD33
DVDD12
R501 0R
SIF_SDA
OSDA0
OSCL0
SIF_SCL
R502
0R
4
3
2
AV12
Digital 1.8V Bypass Caps
DVDD12
L500
600R
DV33
DVDD33
Digital 3.3V Bypass Caps
L501
600R
AV33
AVDD33
Analog 3.3V Bypass Caps
L502
600R
AV33
ADVDD33_1
L503
600R
2
1
B04
F
E
D
C
B
A
1
17953_524_090330.eps
090331
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