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Circuit Diagrams and PWB Layouts
SSB v1: LVDS Receiver
LVDS RECEIVER
B19
DV33A
DV33A
L929
NC\TTL\600R
DV33A_LVDS_RECEIVER
C2202
C2004
C2001
C2006
NC\TTL\0.1U
NC\TTL\0.1U
NC\TTL\0.1U
NC\TTL\0.1U
GND
NC\TTL\0.1U
R23
100R
AN00
AP00
R24
AN11
100R
R2003
100R
AN22
R2004
100R
CLK11-
R2005
100R
AN33
TCM2.0E LA
7.
C2015
C2007
NC\TTL\0.1U
DV33A_LVDS_RECEIVER
U207
T_B5
1
56
RXOUT22
VCC4
55
T_B4
2
RXOUT23
RXOUT21
T_HSYNC
3
54
T_B3
RXOUT24
RXOUT20
4
53
T_B2
GND1
RXOUT19
T_VSYNC
52
5
RXOUT25
GND5
T_DE
6
51
T_B1
RXOUT26
RXOUT18
T_R6
T_B7
7
50
RXOUT27
RXOUT17
49
T_B6
8
LVDSGND1
RXOUT16
AN00
9
48
RXIN0-
VCC3
AP00
T_B0
10
47
RXIN0+
RXOUT15
AN11
46
T_G5
11
RXIN1-
RXOUT14
AP11
12
45
T_G4
RXIN1+
RXOUT13
13
44
LVDSVCC1
GND4
T_G3
14
43
LVDSGND2
RXOUT12
AN22
T_G7
15
42
RXIN2-
RXOUT11
AP22
T_G6
16
41
RXIN2+
RXOUT10
CLK11-
17
40
RXCLKIN-
VCC2
CLK11+
39
T_G2
18
RXCLKIN+
RXOUT9
AN33
19
38
T_G1
RXIN3-
RXOUT8
AP33
20
37
T_G0
RXIN3+
RXOUT7
36
21
LVDSGND3
GND3
T_R5
22
35
PLLGND1
RXOUT6
23
34
T_R7
PLLVCC1
RXOUT5
33
24
T_R4
PWRDN
PLLGND2
RXOUT4
25
32
T_R3
PWRDWN
RXOUT3
T_CLK
26
31
RXCLKOUT
VCC1
T_R2
T_R0
30
27
RXOUT0
RXOUT2
28
29
T_R1
GND2
RXOUT1
V386
GND
DV33A
DV33A
R291
NC\TTL\10K
PWRDN
C
AP11
Q5
PWRDN_EN
B
C143ZT
AP22
E
GND
CLK11+
AP33
45
R293
NC\TTL\33R
T_R7
1
8
R7
T_R6
R6
2
7
T_R5
3
6
R5
T_R4
4
5
R4
R294
NC\TTL\33R
1
8
R3
T_R3
T_R2
2
7
R2
T_R1
3
6
R1
T_R0
4
5
R0
R295
NC\TTL\33R
T_G7
1
8
G7
T_G6
2
7
G6
G5
T_G5
3
6
G4
T_G4
4
5
R296
NC\TTL\33R
T_G3
8
G3
1
T_G2
G2
2
7
T_G1
3
6
G1
T_G0
4
5
G0
R298
NC\TTL\33R
T_B7
1
8
B7
T_B6
B6
2
7
T_B5
B5
3
6
B4
T_B4
4
5
R299
NC\TTL\33R
T_B3
1
8
B3
T_B2
B2
2
7
T_B1
B1
3
6
T_B0
B0
4
5
R290
NC\TTL\33R
8
1
DE
T_DE
2
7
3
6
D_VSYNC
T_VSYNC
T_HSYNC
D_HSYNC
4
5
R292
L239
NC\TTL\33R
T_CLK
120R
CLK
C2011
NC\TTL\16P
GND
B19
VDD_PANEL
P205
C2010
40
39
NC\TTL\0.1U
38
37
R1
36
35
R0
R2
R3
34
33
R5
32
31
R4
R7
R6
30
29
28
27
G0
G1
26
25
G3
G2
24
23
G5
22
21
G4
G7
G6
20
19
18
17
B1
16
15
B0
B3
B2
14
13
B5
12
11
B4
B7
10
9
B6
8
7
D_HSYNC
D_VSYNC
6
5
PANEL_CTL2
4
3
DE
CLK
2
1
GND
I_17950_039.eps
070508
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