Table of Contents
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Features
■
IEEE802.3 10Base-T and IEEE802.3u
100Base-TX, 100Base-FX (ST802RT1B only)
transceiver
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Support for IEEE802.3x flow control
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Provides full-duplex operation in both 100
Mbps and 10 Mbps modes
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Register bit strap during HW reset
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Auto MDI-X for 10/100 Mb/s
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Auto-negotiation
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Provides loop-back mode for diagnostics
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Programmable LED display for operating mode
and functionality signaling
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MII / RMII interface
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MDC / MDIO serial management interface
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Optimized deterministic latency for real-time
Ethernet operation
■
Supports external transformer with turn ratio
1.414:1 on Tx/Rx side
■
Self-termination transceiver for external
components and power saving
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Operation from single 3.3 V supply
■
High ESD tolerance
■
48-pin LQFP 7 x 7 package
■
Extended temp. range: -40 °C to +105 °C
■
Power dissipation < 315 mW (typ)
Applications
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Industrial control
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Factory automation
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High-end peripherals
Table 1.
Device summary
Order codes
ST802RT1AFR
ST802RT1BFR
February 2010
10/100 real-time Ethernet 3.3 V transceiver
■
Building automation
■
Telecom infrastructure
Description
The ST802RT1x is a high-performance fast
Ethernet physical layer interface for 10Base-T,
100Base-TX and 100Base-FX applications. It is
designed using advanced CMOS technology to
provide MII and RMII interfaces for easy
attachment to 10/100 media access controllers
(MAC). The ST802RT1x supports the 100Base-
TX of IEEE802.3u and 10Base-T of IEEE802.3i
and 100Base FX of IEEE 802.3u (B version only).
The ST802RT1x supports both half-duplex and
full-duplex operation at 10 and 100 Mbps
operation. Its operating mode can be set using
auto-negotiation, parallel detection or manual
control. It allows for the support of auto-
negotiation functions for speed and duplex
detection. The automatic MDI / MDIX feature
compensates for the use of a crossover cable.
With auto MDIX, the ST802RT1x automatically
detects what is on the other end of the network
cable and switches the TX & RX pin functionality
accordingly.
Temperature range
- 40 to 105 °C
- 40 to 105 °C
Doc ID 17049 Rev 1
ST802RT1A
ST802RT1B
LQFP48
Package
LQFP48
LQFP48
www.st.com
1/58
58
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Related Manuals for ST ST802RT1A
Summary of Contents for ST ST802RT1A
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Page 1: Table 1. Device Summary
ST802RT1A ST802RT1B 10/100 real-time Ethernet 3.3 V transceiver Features ■ IEEE802.3 10Base-T and IEEE802.3u 100Base-TX, 100Base-FX (ST802RT1B only) transceiver ■ Support for IEEE802.3x flow control ■ Provides full-duplex operation in both 100 Mbps and 10 Mbps modes LQFP48 ■ Register bit strap during HW reset ■... -
Page 2: Table Of Contents
Contents ST802RT1A, ST802RT1B Contents Features ........... 6 Physical layer . - Page 3 ST802RT1A, ST802RT1B Contents 7.16 Automatic MDI / MDIX feature ....... . . 44 7.17...
- Page 4 List of tables ST802RT1A, ST802RT1B List of tables Table 1. Device summary ............1 Table 2.
- Page 5 System diagram of the ST802RT1A/B ........
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Page 6: Features
Features ST802RT1A, ST802RT1B Features Physical layer ● The ST802RT1x integrates the entire physical layer functions of 100Base-TX, 10Base- T and 100Base-FX (B version only) ● Optimized deterministic latency for real-time Ethernet operation ● Provides full-duplex operation in both 100 Mbps and 10 Mbps modes ●... -
Page 7: Device Block Diagram
ST802RT1A, ST802RT1B Device block diagram Device block diagram Figure 1. ST802RT1x block diagram Serial management Serial management MII/RMII INTERFACES MII/RMII INTERFACES INTERFACE INTERFACE CONTROLLER CONTROLLER 10BASE-T 10BASE-T 10BASE-T 10BASE-T 100BASE-TX 100BASE-TX 100BASE-TX 100BASE-TX REGISTERS REGISTERS 100BASE-FX 100BASE-FX 100BASE-FX 100BASE-FX TX CHANNEL... -
Page 8: System And Block Diagrams
System and block diagrams ST802RT1A, ST802RT1B System and block diagrams Figure 2. System diagram of the ST802RT1A/B Figure 3. System diagram of the ST802RT1B in FX mode 8/58 Doc ID 17049 Rev 1... -
Page 9: Pin Configuration
Pin configuration Pin configuration Figure 4. Pin configuration - ST802RT1A 48 47 46 45 44 43 42 41 40 39 38 37 48 47 46 45 44 43 42 41 40 39 38 37 48 47 46 45 44 43 42 41 40 39 38 37... -
Page 10: Figure 5. Pin Configuration - St802Rt1B
Pin configuration ST802RT1A, ST802RT1B Figure 5. Pin configuration - ST802RT1B 48 47 46 45 44 43 42 41 40 39 38 37 48 47 46 45 44 43 42 41 40 39 38 37 48 47 46 45 44 43 42 41 40 39 38 37... -
Page 11: Pin Description
Supply Analog power supply GNDA Ground Analog ground VCCA Supply Analog power supply RESERVED Not used in the ST802RT1A Positive signal detect for 100Base-FX operation (ST802RT1B only) LED_ACT/AN_1 O, S, PU Activity/full-duplex/collision led LED_SPEED/AN_0 O, S, PU Speed LED LED_LINK/AN_EN... -
Page 12: Table 3. Abbreviations
Receive data (MII/RMII)/Phy2 RXD0/PHYADDR1 O, S, PD Receive data (MII/RMII)/Phy1 COL/PHYADDR0 O, S, PU MII collision detection/Phy0 Ground Ground RESERVED Not used in the ST802RT1A Negative signal detect (100Base-FX only) Table 3. Abbreviations Legend Description Input Output Input/output Strap option... -
Page 13: Table 4. Pin Functions Of The St802Rt1X
ST802RT1A, ST802RT1B Pin description Table 4. Pin functions of the ST802RT1x Pin n° Name Type Function Data interface Transmit data. The media access controller (MAC) drives data to the TXD0 ST802RT1x using these inputs. TXD1 txd0 = MII/RMII tx data... - Page 14 PECL logical high level (PECL ) is approximately VCC-0.9 V. HIGH RESERVED in ST802RT1A the pins must be grounded through a 1.2 kΩ resistor Differential receive inputs (100Base-TX, 10Base-T). These pins directly output to the transformer. When MDIX is enabled they can work as TXP/TXN Reference resistor/DC regulator output.
- Page 15 ST802RT1A, ST802RT1B Pin description Table 4. Pin functions of the ST802RT1x (continued) Pin n° Name Type Description 3, 16, 19, 20, GNDA Ground Analog ground Strap pins The ST802RT1x uses many of the functional pins as strap options. The values of these pins are sampled during reset hardware or power-up and used to strap the device into specific modes of operation.
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Page 16: Table 5. Signal Detect
Pin description ST802RT1A, ST802RT1B Table 5. Signal detect Mode Ground Ground TX mode Ground A positive voltage Undefined state Voltage > 0.6 V Voltage > 0.6 V Undefined state PECL (PECL PECL FX mode asserted, but no data valid on the line... -
Page 17: Registers And Descriptors Description
ST802RT1A, ST802RT1B Registers and descriptors description Registers and descriptors description All of the management data control and status registers in the ST802RT1x's register set are accessed via a Write or Read operation on the serial MDIO port. This access requires a protocol described in the MII management interface section. -
Page 18: Register Description
Registers and descriptors description ST802RT1A, ST802RT1B Register description Table 9. Abbreviations Legend Description Read/write Read only Self-clearing Constant STRAP Bit with strap value Latched high Latched low Table 10. RN00 [0d00, 0x00]: Control register Bit name Description Default Type type 1 ->... - Page 19 ST802RT1A, ST802RT1B Registers and descriptors description Table 10. RN00 [0d00, 0x00]: Control register (continued) Bit name Description Default Type type 1 -> Collision test enabled Collision test 0 -> Normal operation Active only in loop-back mode (RN00[14]=1) RESERVED Not used...
- Page 20 Registers and descriptors description ST802RT1A, ST802RT1B be cleared by writing a “0” to bit 10 of the control register, or by resetting the chip. When this bit is read, it returns a “1” when the chip is in isolate mode; otherwise it returns a “0”.
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Page 21: Table 11. Rn01 [0D01, 0X01]: Status Register
ST802RT1A, ST802RT1B Registers and descriptors description Table 11. RN01 [0d01, 0x01]: Status register Bit name Description Default Type type 100BASE-T4 0 -> PHY not able to perform 100BASE-T4 ABILITY Fixed to 0 100BASE-X 1 -> PHY able to perform full-duplex 100BASE-X... -
Page 22: Table 12. Rn02 [0D02, 0X02]: Phy Identifier Register Hi
Type type Organizationally unique identifier (OUI), bits 3..18 15:0 OUI MSBs 0203h OUI bits 1 and 2 are fixed to 0 by standard; ST OUI = 0080E1 Table 13. RN03 [0d03, 0x03]: PHY identifier register Lo Bit name Description Default... -
Page 23: Table 14. Rn04 [0D04, 0X04]: Auto-Negotiation Advertisement Register
ST802RT1A, ST802RT1B Registers and descriptors description Table 14. RN04 [0d04, 0x04]: Auto-negotiation advertisement register Bit name Description Default Type type 1 -> Next page transfer supported Next Page 0 -> Next page transfer not supported RESERVED 1 -> Advertises that this device has detected a remote fault... -
Page 24: Table 15. Rn05 [0D05, 0X05]: Auto-Negotiation Link Partner Ability Register
Registers and descriptors description ST802RT1A, ST802RT1B suppressed from transmission. Resetting the chip restores the default bit values. Reading the register returns the values last written to the corresponding bits, or else the default values if no write has been completed since the last chip reset. Even though bit 9 (advertise 100BASE-T4) is writable, it should never be set since the ST802RT1x does not support T4 operation. -
Page 25: Table 16. Rn06 [0D06, 0X06]: Auto-Negotiation Expansion Register
ST802RT1A, ST802RT1B Registers and descriptors description Reserved: Ignore when read. LP pause: Indicates that the link partner pause bit is set. LP selector field: Bits 4:0 of the link partner ability register reflect the value of the Link partner's selector field. These bits are cleared any time auto-negotiation is restarted or the chip is reset. -
Page 26: Table 17. Rn07 [0D07, 0X07]: Auto-Negotiation Next Page Transmit Register
Registers and descriptors description ST802RT1A, ST802RT1B Table 17. RN07 [0d07, 0x07]: Auto-negotiation next page transmit register Bit name Description Default Type type 1 -> additional next page(s) will follow Next Page 0 -> last page RESERVED 1 -> Message page transmitting Message Page 0 ->... -
Page 27: Table 19. Rn10 [0D16, 0X10]: Rmii-Test Control Register
ST802RT1A, ST802RT1B Registers and descriptors description Next page: Indicates whether this is the last next page. Msg page: Differentiates a message page from an unformatted page. Ack2: Indicates that link partner has the ability to comply with the message. Toggle: Used by the arbitration function to ensure synchronization with the link partner during next page exchange. -
Page 28: Table 20. Rn11 [0D17, 0X11]: Receiver Configuration Information And Interrupt Status Register
Registers and descriptors description ST802RT1A, ST802RT1B Table 20. RN11 [0d17, 0x11]: Receiver configuration information and interrupt status register Bit name Description Default Type type 15:11 RESERVED 00000b 1 -> FX mode set 0 -> FX mode not set FX_MODE If set to '1', auto-negotiation and scrambling is disabled. This... -
Page 29: Table 21. Rn12 [0D18, 0X12]: Receiver Event Interrupts Register
ST802RT1A, ST802RT1B Registers and descriptors description Table 21. RN12 [0d18, 0x12]: Receiver event interrupts register Bit name Description Default Type Type 15:9 RESERVED NOT USED 0000000b INTERRUPT OUTPUT ENABLE: INT_OE_N 1 -> PWRDWN/MDINT is a power-down input 0 -> PWRDWN/MDINT is an interrupt output... -
Page 30: Table 22. Rn13 [0D19, 0X13]: 100Base-Tx Control Register
Registers and descriptors description ST802RT1A, ST802RT1B Table 22. RN13 [0d19, 0x13]: 100Base-TX control register Bit name Description Default Type Type 15:14 RESERVED Disable RX err 1 -> RX error counter disabled counter 0 -> Normal operation 1 -> Auto-negotiation complete Auto Neg Complete 0 ->... -
Page 31: Table 24. Rn18 [0D24, 0X18]: Auxiliary Control Register
ST802RT1A, ST802RT1B Registers and descriptors description Table 24. RN18 [0d24, 0x18]: Auxiliary control register Bit name Description Default Type Type 1 -> Disables jabber detection (10BaseT) Jabber disable 0 -> Normal operation RESERVED 13:8 RESERVED 000000b RESERVED 001b MDIO Power 1 ->... - Page 32 Registers and descriptors description ST802RT1A, ST802RT1B Table 25. RN19 [0d25, 0x19]: Auxiliary status register (continued) Bit name Description Default Type Type 1 -> A fault has been detected via the parallel detection Parallel Detection function (updated on read) Fault 0 -> A fault has not been detected 1 ->...
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Page 33: Table 26. Rn1B [0D27, 0X1B]: Auxiliary Mode 2 Register
ST802RT1A, ST802RT1B Registers and descriptors description Table 26. RN1B [0d27, 0x1B]: Auxiliary mode 2 register Bit name Description Default Type Type 15:12 RESERVED 0000b 11:10 RESERVED 1 -> led_link pad: ON for link_up, BLINK for activity led_speed pad: ON for 100 Mb, OFF for 10 Mb... -
Page 34: Table 27. Rn1C [0D28, 0X1C]: 10Base-T Error And General Status Register
Registers and descriptors description ST802RT1A, ST802RT1B Table 27. RN1C [0d28, 0x1C]: 10Base-T error and general status register Bit name Description Default Type Type 15:14 RESERVED 1 -> MDI-X configuration used MDIX Status 0 -> MDI configuration used 1 -> MDIX force (if not in fx_mode) MDIX Swap 0 ->... -
Page 35: Table 28. Rn1E [0D30, 0X1E]: Auxiliary Phy Register
ST802RT1A, ST802RT1B Registers and descriptors description Table 28. RN1E [0d30, 0x1E]: Auxiliary PHY register Bit name Description Default Type Type 1 -> AN 100Base-TX full-duplex selected HCD 100base-Tx FDX 0 -> AN 100Base-TX full-duplex not selected 1 -> AN 100Base-T4 selected (not supported) 0 ->... -
Page 36: Table 29. Rn1F [0D31, 0X1F]: Shadow Registers Enable Register
Registers and descriptors description ST802RT1A, ST802RT1B HCD 10BaseT: Bits 15:11 of the auxiliary PHY register are five read-only bits that report the highest common denominator (HCD) result of the auto-negotiation process. Immediately upon entering the link pass state after each reset or restart auto-negotiation, only one of these five bits will be a “1”. -
Page 37: Table 30. Rs1B [0D27, 0X1B]: Misc Status/Error/Test Shadow Register
ST802RT1A, ST802RT1B Registers and descriptors description Table 30. RS1B [0d27, 0x1B]: Misc status/error/test shadow register Bit name Description Default Type Type 1 -> MLT3 enabled with no errors (TX100 only) MLT3 Detect 0 -> MLT3 disabled or MLT3 error TX100 CABLE LENGTH (m): 000 <= 20... -
Page 38: Device Operation
Device operation ST802RT1A, ST802RT1B Device operation The ST802RT1x includes a 10/100 Base-T Ethernet transceiver with MII, RMII interfaces for data and control from/to the station management entity (STE). The ST802RT1x integrates the IEEE802.3u compliant functions of PCS (physical coding sub-layer), PMA (physical medium attachment), and PMD (physical medium dependent) for 100Base-TX, and the IEEE802.3 compliant functions of manchester encoding/decoding and transceiver for... -
Page 39: 100Base-Tx Receive Operation
ST802RT1A, ST802RT1B Device operation Wave-shaper and media signal driver: In order to reduce the energy of the harmonic frequency of transmission signals, the device provides the wave-shaper prior to the line driver to smooth out, but maintain symmetric, the rising/falling edge of the transmission signals. -
Page 40: 10Base-T Transmit Operation
Device operation ST802RT1A, ST802RT1B 10Base-T transmit operation In 10Base-T, the device's TX channel includes the parallel-to-serial converter, NRZ to manchester encoder, link pulse generation, and an internal physical ethernet wire interface (Phy). It also provides collision detection and SQE test for half-duplex application. -
Page 41: Power-Down / Interrupt
ST802RT1A, ST802RT1B Device operation Auto-negotiation exchanges information with the network partner using the fast link pulses (FLPs) - a burst of link pulses. FLP’s contain 16 bits of signaling information to advertise all supported capabilities, determined by register RN04 (auto-negotiation advertisement register), to the remote partner. -
Page 42: Led Display Operation
Device operation ST802RT1A, ST802RT1B Write 0180h to RN12 to set INT_EN and INT_OE_N; Write 0010h to RN12 to set LK_DWN_EN; Monitor PWRDWN/MDINT. When the PWRDWN/MDINT pin asserts low, the user should read the RN11 register to see if the LK_DWN is set, i.e. which source caused the interrupt. -
Page 43: Reset Operation
ST802RT1A, ST802RT1B Device operation 7.12 Reset operation There are two ways to reset the ST802RT1x. Hardware reset: the ST802RT1x can be reset via the RESET pin (pin 29). The active low reset input signal is required for at least 1 ms, and at least one transition is required on the MDC (pin 31) to ensure proper reset operation. -
Page 44: Transmit Isolation
Device operation ST802RT1A, ST802RT1B 7.15 Transmit isolation Figure 7. Transmit isolation Transmit isolation isolates the PHY from the MII and Tx +/- interface and is activated by setting bit 5 of the 100Base-TX control register (RN13[5]). As with isolate mode, all MII inputs are ignored and all MII outputs are tri-stated. -
Page 45: Fx Mode Operation
ST802RT1A, ST802RT1B Device operation 7.18 FX mode operation Each port of the ST802RT1x may also be configured for 100BASE-FX transmission over fiber optics via a pseudo-ECL (PECL) interface. In 100Base-Fx mode, scrambling and MLT3-to-binary conversion are bypassed when transmitting, whereas in reception adaptive equalization, binary-to-MLT3 and descrambling are bypassed. -
Page 46: Pecl Transmitter
Device operation ST802RT1A, ST802RT1B These two signals can be either driven by standard CMOS levels or by PECL levels. The data coming from the optical transceiver are PECL signals and need to be converted to CMOS level before being delivered to the data and clock recovery and then to the serial-to- parallel interface to be transmitted to the digital portion. -
Page 47: Pecl Receiver
ST802RT1A, ST802RT1B Device operation Figure 9. Implementation of the PECL TX section 7.21 PECL receiver The data signals coming from the optical transceiver are in PECL format and need to be converted to CMOS level before being transmitted to the data and clock recovery, and to the digital portion. -
Page 48: Far-End-Fault
Section 7.13. The preamble is followed by a 2-bit start of frame (ST), consisting of a transition to logic 0 and then back to logic 1, after which the operation code (OP) is transmitted to distinguish between read and write operations. -
Page 49: Electrical Specifications And Timings
ST802RT1A, ST802RT1B Electrical specifications and timings Electrical specifications and timings Table 34. Absolute maximum ratings Parameter Value Unit Supply voltage (V -0.5 to 4 Input voltage -0.5 to V + 0.5 Output voltage -0.5 to V + 0.5 Storage temperature -65 to 150 °C... - Page 50 Electrical specifications and timings ST802RT1A, ST802RT1B Table 35. General DC specification (continued) Symbol Parameter Test conditions Min. Typ. Max. Unit XTAL conditions X1 duty cycle X1 frequency 25/50/125 X1 tolerance X1 load capacitance X1CL 10Base-T normal link pulse (NLP) Tnps...
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Page 51: Figure 11. Normal Link Pulse Timings
ST802RT1A, ST802RT1B Electrical specifications and timings Figure 11. Normal link pulse timings Figure 12. Fast link pulse timing Doc ID 17049 Rev 1 51/58... -
Page 52: Figure 13. Mii Management Clock Timing
Electrical specifications and timings ST802RT1A, ST802RT1B Figure 13. MII management clock timing 52/58 Doc ID 17049 Rev 1... -
Page 53: Package Mechanical Data
ST802RT1A, ST802RT1B Package mechanical data Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. -
Page 54: Table 36. Lqfp48 Mechanical Data
Package mechanical data ST802RT1A, ST802RT1B Table 36. LQFP48 mechanical data Dim. Min. Typ. Max. 1.60 0.05 0.15 1.35 1.45 0.17 0.22 0.27 0.09 0.20 8.80 9.20 6.80 7.20 5.50 8.80 9.20 6.80 7.20 5.50 0.50 0.45 0.60 0.75 0° 3.5°... -
Page 55: Figure 14. Dimensions Of The Lqfp48 Package
ST802RT1A, ST802RT1B Package mechanical data Figure 14. Dimensions of the LQFP48 package 0110596 Doc ID 17049 Rev 1 55/58... -
Page 56: Figure 15. Lqfp48 Footprint Recommended Data (Mm.)
Package mechanical data ST802RT1A, ST802RT1B Figure 15. LQFP48 footprint recommended data (mm.) 56/58 Doc ID 17049 Rev 1... -
Page 57: Revision History
ST802RT1A, ST802RT1B Revision history Revision history Table 37. Document revision history Date Revision Changes 02-Feb-2010 Initial release. Doc ID 17049 Rev 1 57/58... - Page 58 No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein.
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