Sony NW-A1000 Service Manual page 40

NW-A1000
IC6005 SCF5250 (MAIN SYSTEM CONTROLLER)
Pin No. Pin Name
1 DATA16
2 A23
3 PAD_VDD
4 A22
5 to 8 A21 to A18
9 PAD_GND
10 A17
11 to 14 A16 to A13
15 PAD_VDD
16, 17 A12, A11
18 CORE_VDD
19 CORE_GND
20, 21 A10, A9
22 to 25 A8 to A5
26 PAD_GND
27 A4
28 to 30 A3 to A1
31 CS0
32 XRW
33 OSC_PAD_VDD
34 CRIN
35 CROUT
36 OSC_PAD_GND
37 PLL_CORE1_VDD
38 CORE_VDD
39 CORE_GND
40 PLL_CORE1_GND
41 OE
42 IDE_DIOW
43 IDE_IOPDY
44 IDE_DIOR
45 BUFFENB2
46 GSEN_SEL1
47 TA
48 WAKEUP
49 XRESET_LCD
50 SPI_CS2
51 PAD_VDD
WAKEUP_DENDE
52
53 DENDE_SREQ
54 DATA_READY
55 CS1
56 MULTI_SI
57 MULTI_SCK
58 MULTI_SO
59, 60 SPI_CS1, SPI_CS0
40
I/O
I/O
Two-way data bus with the SD-RAM and NOR flash memory
O
Address signal output to the SD-RAM
-
Power supply terminal (+3V) (for I/O)
O Address signal output to the SD-RAM
O
Address signal output to the SD-RAM and NOR flash memory
-
Ground terminal (for I/O)
O
Address signal output to the NOR flash memory
O Address signal output to the SD-RAM and NOR flash memory
-
Power supply terminal (+3V) (for I/O)
O
Address signal output to the SD-RAM and NOR flash memory
-
Power supply terminal (+1.1V) (for core)
- Ground terminal (for core)
O
Address signal output to the SD-RAM and NOR flash memory
O
Address signal output to the USB controller and NOR flash memory
-
Ground terminal (for I/O)
O Address signal output to the USB controller and NOR flash memory
O
Address signal output to the USB controller, NOR flash memory and PLD
O
Chip select signal output to the NOR flash memory
O
Read/write control signal output to the NOR flash memory, PLD and EL module
- Power supply terminal (+3V) (for OSC)
I
Main system clock input terminal (22.5792 MHz)
O
Main system clock output terminal (22.5792 MHz)
-
Ground terminal (for OSC)
- Power supply terminal (+1.1V) (for PLL)
-
Power supply terminal (+1.1V) (for core)
-
Ground terminal (for core)
-
Ground terminal (for PLL)
O Read signal output to the NOR flash memory, PLD and EL module
O
Write signal output to the USB controller
I
Wait signal input from the USB controller
O
Read signal output to the USB controller
O BUFFENB signal output terminal Not used
O
G-sensor axis selection signal output terminal
I
Access complete signal input terminal Not used
I
Wake-up signal input from the USB controller
O Reset signal output to the EL module "L": reset
O
Chip select signal output for serial control to the PLD
-
Power supply terminal (+3V) (for I/O)
O
Wake-up signal output to the PLD
O Request signal output to the PLD
I
Ready signal input from the PLD
O
Chip select signal output to the PLD
I
Serial data input from the PLD and power control
O Serial data transfer clock signal output to the PLD
O
Serial data output to the real time clock and PLD
O
Chip select signal output for serial control to the PLD
Description