Sony NW-A1000 Service Manual page 36

NW-A1000
• IC Pin Function Description
IC3101 CXR710160-215GH (SUB SYSTEM CONTROLLER)
Pin No. Pin Name
1 LRCK
2 BCK
3 VDIOCD0
4 PCMD
5 DVDD4
6 TEST8
7 TEST7
8 DVDD0
9 DVSS0
10 VDIO0
11 VDIOCD1
12 XRDE
13 BCK0
14 LRCK0
15 PCMD0
16 EVA
17 KCLK
18 KCS
19 VDIO01
20 KDO
21 KDI
22 KRB
23 DVDD1
24 DVSS3
25 AVDPLL
26 AVSPLL
27 AVSOSC
28 AVDMO
29 EXTAL
30 XTAL
31 XIN
32 OSSEL
33 NRST
34
PF0
35 PF1
36 PF2
37 PF3
38 PC0
39 VDIOCD2
40 PC1
41 PC2
42 PC3
43 DVDD2
44 DVSS2
45 to 48 PE0 to PE3
49 VDIO2
36
I/O
I L/R sampling clock signal input from the PLD
I
Bit clock signal input from the PLD
-
Power supply terminal (+1.8V) (for CD interface and I/O)
I
Audio data input from the PLD
- Power supply terminal (+1.3V)
O
Output terminal for the test
I
Input terminal for the test
-
Power supply terminal (+1.3V)
- Ground terminal
-
Power supply terminal (+1.8V) (for I/O)
-
Power supply terminal (+1.8V) (for CD interface and I/O)
I
Ready/busy selection signal input from the PLD "L": ready, "H": busy
O Bit clock signal output to the PLD
O
L/R sampling clock signal output to the PLD
O
Audio data output to the PLD
I
EVA mode selection signal input terminal
O Serial data transfer clock signal output terminal Not used
O
Chip select signal output terminal Not used
-
Power supply terminal (+1.8V) (for I/O)
O
Serial data output terminal Not used
I Serial data input terminal Not used
O
Ready/busy selection signal output terminal Not used
-
Power supply terminal (+1.3V)
-
Ground terminal
- Power supply terminal (+3V) (for PLL)
-
Ground terminal (for PLL)
-
Ground terminal (for OSC)
-
Power supply terminal (+3V) (for OSC)
I Main system clock input terminal (22.5792 MHz)
O
Main system clock output terminal (22.5792 MHz)
I
External clock input terminal Not used
I
External clock control signal input terminal Not used
I Reset signal input from the PLD "L": reset
I
Wake-up signal input from the PLD
O
Ready signal output to the PLD
I
Interrupt request signal input from the PLD
O
Interrupt request signal output to the PLD
I
Serial data transfer clock signal input from the PLD
-
Power supply terminal (+1.8V) (for CD interface and I/O)
O
Serial data output to the PLD
I
Serial data input from the PLD
O
Chip select signal output to the PLD
-
Power supply terminal (+1.3V)
-
Ground terminal
I/O
Not used
-
Power supply terminal (+1.8V) (for I/O)
Description