JVC KD-S845 Service Manual page 31

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• Pin function
Pin No. Symbol I/O
1 /RESET I Hard reset input terminal(H:Normal
operation L: Reset)
2 MiMD I Micon I/F mode select input terminal
3 AD0 O External SRAM address output 0 terminal
4 AD1 O External SRAM address output 1 terminal
5 MiDio I/O Micon I/F data input/output terminal
6 /MiCK I Micon I/F clock input terminal
7 AD2 O External SRAM address output 2 terminal
8 VDDT - Digital power supply (3.3V)
9 SDo O Data output terminal
10 AD3 O External SRAM address output 3 terminal
11 AD4 O External SRAM address output 4 terminal
12 SDi0 I Data input terminal 0
13 BCKiA I Bit clock input terminal A
14 LRCKiA I LR clock input terminal A
15 AD5 O External SRAM address output 5 terminal
16 CE O External SRAM chip enable terminal
17 OE O External SRAM output enable terminal
18 VDD - Digital power supply (2.5V)
19 STANB I Standby mode control terminal
Y
20 VSS - Digital GND
21 VSSL - DAC Lch GND
22 VRAL - DAC Lch reference voltage terminal
23 LO O DAC Lch output terminal
24 VDAL - DAC Rch power supply terminal(2.5V)
TE
L 13942296513
25 VDAR - DAC Lch power supply terminal(2.5V)
26 RO O DAC Rch output terminal
27 VRAR - DAC Rch reference voltage terminal
28 VSSR - DAC Rch GND
29 TESTP I Test terminal
30 CKS I VCO select terminal
31 AD12 O External SRAM address output 12
terminal
32 AD11 O External SRAM address output 11
terminal
33 AD10 O External SRAM address output 10
terminal
34 AD9 O External SRAM address output 9 terminal
35 VDDT - Digital power supply terminal (3.3V)
36 AD8 O External SRAM address output 8 terminal
37 AD7 O External SRAM address output 7 terminal
38 AD6 O External SRAM address output 6 terminal
39 REQ O Squeeze request terminal to host
40 VSS - Digital GND
41 AD13 O External SRAM address output 13
terminal
42 AD14 O External SRAM address output 14
terminal
43 WR O External SRAM write signal
44 AD16 O External SRAM address output 16
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terminal
45 AD15 O External SRAM address output 15
terminal
.
46 io0 I/O External SRAM data input/output 0
terminal
47 io1 I/O External SRAM data input/output 1
terminal
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Pin No. Symbol I/O
48 VSS -
49 io2 I/O External SRAM data input/output 2
50 io3 I/O External SRAM data input/output 3
51 io4 I/O External SRAM data input/output 4
52 VDD -
53 io5 I/O External SRAM data input/output 5
54 io6 I/O External SRAM data input/output 6
55 io7 I/O External SRAM data input/output 7
56 VSSP -
57 Pdo O PLL phase error detection signal output
58 Vcoi I
59 VDDP -
60 Cko O 16.934 MHz clock output terminal
61 VDDX -
62 Xi I
63 Xo O Connection terminal for oscillator (output)
64 VSSX -
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Description
Digital GND
terminal
terminal
terminal
Digital power supply (2.5V) terminal
terminal
terminal
terminal
VCO GND
terminal
VCO control voltage input terminal
VCO power supply
Power supply (2.5V) terminal for oscillator
Connection terminal for oscillator (input)
GND for oscillator
0 5 8 2 9 9 4 2 8
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(No.49858)1-31
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