2-1-6 512K X 16 Bit X 2 Banks Synchronous DRAM (A43L0616)
Features
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JEDEC standard 3.3V power supply
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LVTTL compatible with multiplexed address
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Dual banks / Pulse RAS
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MRS cycle with address key programs
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All inputs are sampled at the positive going edge of the system clock
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Burst Read Single-bit Write operation
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DQM for masking
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Auto & self refresh
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64ms refresh period (4K cycle)
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50 Pin TSOP (II)
Pin Configuration
CAS Latency (2,3)
Burst Length (1,2,4,8 & full page)
Burst Type (Sequential & interleave)
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