Sony CDX-M700R Service Manual page 39

Pin No. Pin Name
63 RVDT
64 24/23BIT
65 DVDD
66 DVSS
67 – 69 SO1 – SO3
70 SOUT
71 DATA
72, 73 SI1, SI3
74 SIN
75 BCK
76 LRCK
77 MST/SLV
78 DVDD
79 PLLGND
80 PLLENA
81 22 MHz
82 PLLCNT
83 PLLVDD
84 DGND
85 – 94 NIL
95 DVDD
96 DRAMGND
97 – 99 NIL
100 DRAMVDD
I/O
I Serial data input from the master controller (IC801)
Serial data 24/32 bit slot selection signal input terminal
I
"L": 24 bit slot, "H": 32 bit slot (validity at slave mode) (fixed at "L" in this set)
— Power supply terminal (+3.3 V) (digital system)
— Ground terminal (digital system)
O Serial data output terminal (Not used.)
O Serial data output terminal (Not used.)
I Serial data input terminal
I Serial data input terminal Not used (fixed at "L")
I Serial data input terminal Not used (fixed at "L")
I Bit clock signal (2.8224 MHz) input terminal
I L/R sampling clock signal (44.1 kHz) input terminal
Bit clock (BCK) and L/R sampling clock (LRCK) signal master/slave mode selection
I
signal input from the master controller (IC502) "L": master mode, "H": slave mode
— Power supply terminal (+3.3 V) (digital system)
— Ground terminal (PLL system)
I PLL enable signal input terminal Normally: fixed at "L"
O PLL clock signal output terminal (22.5792 MHz) (Not used.)
PLL clock output control signal input from the master controller (IC801)
I At "L" is input: fixed at "L" is PLCLK (pin ia)
At "H" is input: PLL clock signal output from the PLCLK (pin ia)
— Power supply terminal (+3.3 V) (PLL system)
— Ground terminal (digital system)
I Input terminal for the test Normally: fixed at "L"
— Power supply terminal (+3.3 V) (digital system)
— Ground terminal (for D-RAM)
I Input terminal for the test Normally: fixed at "L"
— Power supply terminal (+3.3 V) (for D-RAM)
Pin Description
39