Samsung SENS R60 Plus Service Manual page 24

4
SAMSUNG PROPRIETARY
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO'S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
D
C
R756 1M
nostuff
2801-004667
14.31818MHz
Y502
C789
0.022nF
MINIPCIE3_CLKREQ#
B
FSA FSB FSC
HOST CLK
CPU BSEL0 BSEL1 BSEL2
0 0 0 266 MHz
0 0 1 333 MHz
A
0 1 0 200 MHz
0 1 1 400 MHz
1 0 0 133 MHz Celeron 533MHz
1 0 1 100 MHz
1 1 0 166 MHz
Yonah 667MHz
1 1 1 RSVD
4
3
Pt decoupling CAPS close to Clock Chip power pin
TP18453 TP18378
P3.3V
B521
BLM18PG181SN1
TP18452
C786 C787 C790
4700nF 100nF 100nF
6.3V 10V 10V
nostuff
TP18456
TP18455
ITP3_DBRESET#
9-B2 20-A4 20-C3 54-B3
CLK3_PWRGD#
40-C3 49-C4 54-B4
CHP3_CPUSTP#
19-A4 54-C4
SMB3_CLK
C788 17-B2 17-B4 20-A4 20-C3 33-C4 35-C2 35-C2 54-D2 54-D2
SMB3_DATA
0.022nF 17-B2 17-B4 20-A4 20-C3 33-C4
TP18457
R753 0
EXP3_CLKREQ#
33-C4 54-C3 R732 0
35-C4 54-B3
R645
475
1%
3
P3.3V
BLM18PG181SN1
B515
TP18379 TP18454
C715
10000nF
6.3V
Change to Low cost cap
TP18458
C718
U517
10nF
ICS951461
56 50
VDDCPU VDDA
44 49
VDD_SRC1 GNDA
28
VDD_SRC2
23 VDD_SRC3 58 R651
CPUT0
14 57 R652
VDD_SRC4 CPUC0
4 CPUT1 54 R649
VDD_48
39 53 R646
VDD_ATIG CPUC1
1 52
VDD_REF CPUT2
51
CPUC2
55 47 R644
GND_CPU SRCCLKT0
45 46 R642
GND_SRC1 SRCCLKC0
29 GND_SRC2 43 R640
ATIGCLKT0
22 42 R638
GND_SRC3 ATIGCLKC0
15 41 R744
GND_SRC4 ATIGCLKT1
7 40 R741
GND_48 ATIGCLKC1
38 37
GND_ATIG ATIGCLKT2
64 GND_REF 36
ATIGCLKC2
35
ATIGCLKT3
34
ATIGCLKC3
2 30 R735
X1 SRCCLKT1
31 R733
SRCCLKC1
3 X2 SRCCLKT2 26 R740
27 R737
SRCCLKC2
24
SRCCLKT3
25
SRCCLKC3
20
SRCCLKT4
60 21
RESET_IN* SRCCLKC4
8 18 R748
VTTPWRGD*_PD SRCCLKT5
59 CPU_STOP* SRCCLKC5 19 R745
16
SRCCLKT6
17
SRCCLKC6
12
SRCCLKT7
9 13
SMBCLK SRCCLKC7
10
SMBDAT
48 6 R754
IREF 48MHZ_1
48MHZ_0 5
11
CLKREQA*
32 63 R694
CLKREQB* FSLA_REF0
33 62 R693
CLKREQC* FSLB_REF1
61 R650
FSLC_REF2
R696
R695
Compatible Components
Silego : SLG84610
Place all te serias termination resistor as close as Clock Chip as possible
FSA, FSB, FSC of Clock chip are low thershold inputs
Vih_fs_min = 0.7V
Vil_fs_max - 0.35V
2
P3.3V
C717
10000nF
6.3V
Route all CLK1 signal as different pair rule
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
R752 33
R749 33
33
2.2K
2.2K
2.2K
33
33
C869
0.022nF
2
1
D
9-D4
CLK0_HCLK0
9-D4
CLK0_HCLK0#
15-B4
CLK0_HCLK1
15-B4
CLK0_HCLK1#
CLK1_PCIEICH
13-B3
CLK1_PCIEICH#
13-B3
CLK1_NBSRC
13-B3
CLK1_NBSRC#
13-B3
CLK1_PEG
CLK1_PEG#
C
CLK1_PCIELOM
41-D4
CLK1_PCIELOM#
41-D4
CLK1_MINIPCIEA
35-C4
CLK1_MINIPCIEA#
35-C4
CLK1_PCIERCLK
19-D4
CLK1_PCIERCLK#
19-D4
CLK1_EXPCARD
33-C4
CLK1_EXPCARD#
33-C4
CLK3_USB48
20-D2
CPU1_BSEL0
9-C4
CPU1_BSEL1
9-C4
CPU1_BSEL2
9-C4
CLK3_NB14M
54-C4 15-B4
CLK3_ICH14
B
54-C4 20-C3
A
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ELECTRONICS
1