Wiznet W5300 Porting Manual page 9

tADDRs Address Setup Time after /CS and /WR low
tADDRh Address Hold Time after /CS or /RD high
tCS /CS low Time
tCSn /CS next Assert Time
tWR /WR low time
tDATAs Data Setup Time after /WR low
tDATAf Data Fetch Time
tDATAh Data Hold Time after /WR high
The Bus access timing of MCU should be set suitably. If the access cycle time sets shorter than
65ns, the data is broken. However the access cycle time sets too long, it comes to be the low
data access speed of W5300. So we must set the access cycle time to a little longer than 65ns
but the closest time to 65ns.
S3C2410 which is the MCU of W5300E01-ARM sets the access timing by using
TACS/TCOS/TACC/TACP/TCOH/TCAH registers. Where, register of access cycle setting is TACC.
Therefore TACC sets according to previous condition and other registers sets '0'. Since the bus
clock of W5300E01-ARM is 100 MHz, the suitable access cycle clock for previous condition is
'7'. But it disallows in S3C2410. So we should set the access cycle clock to '8'. (TACC = 5)
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Description
< Fig 4. W5300 WRITE Timing >
< Fig 5. W5300E01-ARM BUS Access Timing >
Min
-
-
50 ns
28 ns
50 ns
7 ns 7ns + 7XPLL_CLK
14 ns
7 ns
W5300 Linux Driver Porting Guide | 9 page
Max
7 ns
-
-
tWR-tDATAs
-