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IC BLOCK DIAGRAM/ TERMINAL DESCRIPTION
Q703: S-80130CLMC-JKM VOLTAGE DETECTOR (13.0V CMOS, Active L: out)
Pin Layout
5
1
TE
L 13942296513
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.
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4
Top view
2
3
Block Diagram
VDD
DELAY CIRCUIT
VREF
VSS
x
ao
y
i
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8
Detection voltage: 3.0V +/-2%
Delay time: 200ms typ.
Pin Description
No.
Symbol
Description
1
DS
ON/OFF switch for delay time
2
VSS
GND
*1
3
NC
Non-connection
4
OUT
Voltage detection output pin
5
VDD
Voltage input pin
*1. NC pin is electrically open.
Q Q
3
6 7
1 3
OUT
Oscillator
counter
timer
DS
u163
.
2 9
9 4
2 8
1 5
0 5
8
2 9
9 4
m
co
DV-SP501
9 9
2 8
9 9
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