1. Manuals
  2. Brands
  3. Force Manuals
  4. Motherboard
  5. SYS68K/CPU-30 R4
  6. Technical reference manual

Force SYS68K/CPU-30 R4 Technical Reference Manual

Hide thumbs
Table of Contents

Advertisement

Quick Links

Enlarged version
SYS68K/CPU-30 R4
Technical Reference Manual
Edition No. 2
February 1997
P/N 204030
FORCE COMPUTERS Inc./GmbH
All Rights Reserved
This document shall not be duplicated, nor its contents used
for any purpose, unless express permission has been granted.
Copyright by FORCE COMPUTERS

Advertisement

Table of Contents
loading
Need help?

Need help?

Do you have a question about the SYS68K/CPU-30 R4 and is the answer not in the manual?

Questions and answers

Related Manuals for Force SYS68K/CPU-30 R4

Summary of Contents for Force SYS68K/CPU-30 R4

  • Page 1 SYS68K/CPU-30 R4 Technical Reference Manual Edition No. 2 February 1997 P/N 204030 FORCE COMPUTERS Inc./GmbH All Rights Reserved This document shall not be duplicated, nor its contents used for any purpose, unless express permission has been granted. Copyright by FORCE COMPUTERS...

  • Page 2: Table Of Contents

    Overview of the SYS68K/CPU-30 R4 ........
  • Page 3 SYS68K/CPU-30 R4 Memory Map ........
  • Page 4 Table of Contents 3.4.5 Shared RAM Addressing ......... . 40 3.4.6 Shared RAM Performance.
  • Page 5 Table of Contents 3.8.5 Summary of the RTC ..........57 The DUSCC 68562 .
  • Page 6 Table of Contents 3.10.19 Floppy Drive Ready Signal at PI/T #2....... . 77 3.10.20 Floppy Drive Write Protect Signal at PI/T #2 .
  • Page 7 Table of Contents 3.13.2.2The LANCE Interrupt........90 3.13.2.3Summary of the LANCE .
  • Page 8 Circuit Schematics of SYS68K/CPU-30 R4 ........115...
  • Page 9 Table of Contents 4.2.5 FDC37C65C........... 121 4.2.6 LANCE Am79C90.
  • Page 10 FMB - FORCE Message Broadcast ........
  • Page 11 Table of Contents Benchmark Source Code ..........165 Modifying Special Locations in ROM .
  • Page 12 SYS68K/CPU-30 R4 Technical Reference Manual Table of Contents List of Figures Figure 1. Diagram of the CPU-30 R4 (Top View) ................13 Figure 2. Diagram of the CPU-30 R4 (Bottom View) ..............14 Figure 3. Front Panel ........................19 Figure 4.
  • Page 13 Signal Assignment of the VME P2 Connector ..............24 Table 9. Rotary Switches ....................... 25 Table 10. SYS68K/IOBP-1 Pin Assignment ................... 26 Table 11. SYS68K/CPU-30 R4 Memory Map ................30 Table 12. Exception Vector Assignments..................33 Table 13. Used Device Types for the Shared Memory..............38 Table 14.

  • Page 14: Introduction

    CAUTION: Before installing the board, please read the complete installation instructions. 1.1.1 SYS68K/CPU-30 When purchased from FORCE, this set includes the SYS68K/CPU-30 R4 R4 Technical Technical Reference Manual, a copy of the circuit schematics, and copies Reference Manual of the following data sheets:...

  • Page 15: Overview Of The Sys68K/Cpu-30 R4

    68030 microprocessor and the VMEbus. The CPU board also includes an enhanced Floating Point Coprocessor 68882. The board design utilizes all of the features of the powerful FORCE Gate Array FGA-002. The CPU-30 R4 provides an A32/D32 VMEbus interface including...
  • Page 16 SYS68K/CPU-30 R4 Technical Reference Manual Introduction Coprocessor - 68882 with 25 MHz frequency - Pin- and SW-compatible with the MC68881 Main Memory - 4, 8, 16, or 32 Mbyte of shared DRAM on-board - Byte parity VMEbus Interface - Via FGA-002 in the 304-pin PQFP package...
  • Page 17 Introduction SYS68K/CPU-30 R4 Technical Reference Manual System Flash Memory - 4 Mbyte Flash Memory is default configuration - Up to 8 Mbyte Flash Memory - 32-bit wide - Reprogrammable on-board - HW write protection Ethernet Interface - Via AM79C90 - Compatible with IEEE 802.3 Rev.0...

  • Page 18: Duscc

    - One port available on standard 3-row VMEbus P2 connector. - All channels support RS-232 or RS-422 via the FORCE hybrids FH-00x – as factory option also RS-485. - RS-422 – and as factory option also RS-485 – terminations via...
  • Page 19 Introduction SYS68K/CPU-30 R4 Technical Reference Manual - Real-Time Clock 72423 - IRQ capability - Time of day and date counter included (year, month, week, day) - Built-in quartz oscillator - 12 hr/24 hr clock switch-over - Automatic leap year setting...

  • Page 20: Specifications

    SYS68K/CPU-30 R4 Technical Reference Manual Introduction 1.3 Specifications Table 1: Specifications for the CPU-30 R4 Board CPU type 68030 CPU clock frequency 25 MHz Shared DRAM capacity with parity CPU-30ZBE R4 4 Mbyte CPU-30BE/8 R4 8 Mbyte CPU-30BE/16 R4 16 Mbyte...
  • Page 21 Introduction SYS68K/CPU-30 R4 Technical Reference Manual Table 1: Specifications for the CPU-30 R4 Board (Continued) RESET and ABORT switches VMEPROM firmware installed on all board versions 512 Kbyte Power requirements + 5 V max typical 2.3A +12 V max typical 0.4A - 12 V max typical 0.1A...

  • Page 22: Ordering Information

    SYS68K/CPU-30 R4 Technical Reference Manual Introduction 1.4 Ordering Information This page contains a list of the product names and their descriptions. Table 2: Ordering Information Product Name Product Description CPU-30ZBE Rev. 4 68030/68882 CPU, 25 MHz, 4 Mbyte shared DRAM, 4 Mbyte Flash, SCSI, Ethernet, Floppy disk, 4 serial I/O ports, 32-bit VME- bus interface, VMEPROM firmware.

  • Page 23: History Of Manual Publication

    Introduction SYS68K/CPU-30 R4 Technical Reference Manual 1.5 History of Manual Publication Below is a description of the publication history of this SYS68K/CPU-30 R4 Technical Reference Manual. Table 3: History of Manual Edition No. Description Date First Print February 1996 Rotary switch description February 1997 in the section “VMEPROM”...

  • Page 24: Installation

    This Installation Section provides guidelines for powering up the SYS68K/CPU-30 R4 board. The Installation Section, which you have in your hand now, appears both as Section 2 of the SYS68K/CPU-30 R4 Technical Reference Manual and as a stand-alone Installation Guide.

  • Page 25: Board Installation

    SEE ALSO: Before powering up check that the default switch settings are correct as outlined in Section 2.3 ‘Default Switch Settings’. 2.2 Location Diagrams of the SYS68K/CPU-30 R4 Board A location diagram showing the important components on the top side of the CPU-30 R4 appears on the next page.

  • Page 26: Figure 1. Diagram Of The Cpu-30 R4 (Top View)

    SYS68K/CPU-30 R4 Technical Reference Manual Installation Figure 1: Diagram of the CPU-30 R4 (Top View) Reset Switch FORCE Gate Array Abort Switch FGA-002B Run LED BM LED Rotary Switches MC68030 Processor AUI- Ethernet MC68882 Boot EPROM Coprocessor 7992 Optional Boot EPROM...

  • Page 27: Figure 2. Diagram Of The Cpu-30 R4 (Bottom View)

    Installation SYS68K/CPU-30 R4 Technical Reference Manual Figure 2: Diagram of the CPU-30 R4 (Bottom View) NOTE: Pin 1 is always located near the diagonal line shown on each switch and the OFF side of the switch is also always located near the diagonal line.

  • Page 28: Default Switch Settings

    SYS68K/CPU-30 R4 Technical Reference Manual Installation 2.3 Default Switch Settings The following table shows the default settings for all the switches on the board. Please make sure you check the default settings before powering up the board. SEE ALSO: For the position of the switches on your CPU-30 R4 board, please see Figure 2, “Diagram of the CPU-30 R4 (Bottom View),”...
  • Page 29 Installation SYS68K/CPU-30 R4 Technical Reference Manual Table 4: Default Switch Settings (Continued) Diagram of Switch Default Switches Function with Default Setting Setting SWITCH 7 SW7-1 OFF = RESET Switch enabled = RESET Switch disabled SW7-2 OFF = ABORT Switch enabled...
  • Page 30 SYS68K/CPU-30 R4 Technical Reference Manual Installation Table 4: Default Switch Settings (Continued) Diagram of Switch Default Switches Function with Default Setting Setting SWITCH 12 SW12-1 OFF = Serial channel 1 for RS-232 Hybrid FH-002 = Serial channel 1 for RS-422 Hybrid FH-003...

  • Page 31: Front Panel

    Installation SYS68K/CPU-30 R4 Technical Reference Manual 2.4 Front Panel The table below outlines the layout on the front panel. Additionally, there is a drawing of the front panel on the next page. The front panel devices are briefly described on the pages following the drawing.

  • Page 32: Figure 3. Front Panel

    SYS68K/CPU-30 R4 Technical Reference Manual Installation Figure 3: Front Panel SYS68K/ CPU-30 R4 RESET RESET and ABORT Keys ABORT Status LEDs Rotary Switches 15-pin D-Sub Connector 9-pin D-Sub Connector 9-pin D-Sub Connector 9-pin D-Sub Connector Page 19...

  • Page 33: Reset And Abort Keys

    Installation SYS68K/CPU-30 R4 Technical Reference Manual 2.4.1 RESET and The RESET key generates an on-board reset. The ABORT key generates ABORT Keys an IRQ on a programmable level. Both keys can be disabled via the switches described below: SW7-1 Description...

  • Page 34: Serial I/O Channels

    The CPU-30 R4 has three serial I/O channels available via 9-pin D-Sub connectors on the front panel. All channels will support RS-232, RS-422 and RS-485 interfaces via the FORCE hybrids FH-00x. The default configuration is RS-232. The following table shows the pinout of the serial I/O channels for RS-232.

  • Page 35: Aui-Ethernet

    Installation SYS68K/CPU-30 R4 Technical Reference Manual 2.6 AUI-Ethernet The AUI-Ethernet Interface is available on the front panel via a 15-pin D-Sub connector. The unique Ethernet address is displayed by the banner when entering the FGA Boot debugger. FGA Boot also provides a utility function to get the CPU board’s Ethernet address: “#40 (0x28) Get Ethernet Number”.

  • Page 36: Scsi

    SYS68K/CPU-30 R4 Technical Reference Manual Installation 2.7 SCSI The MB87033/34 provides an 8-bit single-ended SCSI interface. It is routed to the VMEbus P2 connector. The termination is switch selectable and "TERMPWR" is supported. The following switches control the SCSI termination.

  • Page 37: Connector Pinout For Vmebus P2

    RxD Port 4 PIT1 C7 PIT1 H4 CTS Port 4 TxD Port 4 GND Port 4 DTR Port 4 NOTE: The signals marked in parenthesis are only available with the use of FH-002 hybrids, which are available at FORCE COMPUTERS. Page 24...

  • Page 38: Introduction To Vmeprom Firmware

    MODE 1 MODE 2 The different functions of the rotary switches are described in detail in the VMEPROM section of the SYS68K/CPU-30 R4 Technical Reference Manual. Correct Operation To test the correct operation of the CPU board, the following command must be typed in: # SELFTEST <CR>...

  • Page 39: The Sys68K/Iobp-1

    SYS68K/CPU-30 R4 Technical Reference Manual 2.11 The SYS68K/IOBP-1 FORCE COMPUTERS offers an IOBP-1 back panel for easy connection of I/O signals through the VMEbus P2 connector. This board can be plugged into the VMEbus P2 connector of a VMEbus board which carries the SCSI, FDC, and serial I/O signals on the VMEbus P2.
  • Page 40 SYS68K/CPU-30 R4 Technical Reference Manual Installation Table 10: SYS68K/IOBP-1 Pin Assignment (Continued) PIN No. PIN No. Row A Row B Row C IOBP-1 VMEbus Signal Mnemonic Signal Mnemonic Signal Mnemonic Page 27...
  • Page 41 Installation SYS68K/CPU-30 R4 Technical Reference Manual Page 28...

  • Page 42: Hardware Description

    68030 microprocessor and the VMEbus. The CPU board also includes an enhanced Floating Point Coprocessor 68882. The board design utilizes all of the features of the powerful FORCE Gate Array FGA-002. Besides the CPU-30 R4, there will be a CPU-30Lite R4 without a coprocessor, a SCSI, an Ethernet, and a floppy disk interface.

  • Page 43: Sys68K/Cpu-30 R4 Memory Map

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.1 SYS68K/CPU-30 R4 Memory Map Table 11: SYS68K/CPU-30 R4 Memory Map Access Address range Device width DRAM: contributing to shared 32/16/8 0000.0000 …00xF.FFFF RAM, address range depends on memory capacity VME A32 extended address space 32/16/8 00 xx.
  • Page 44 SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description Table 11: SYS68K/CPU-30 R4 Memory Map (Continued) Access Address range Device width DUSCC1 FF80.2000 …FF80.21FF FF80.2200 DUSCC2 …FF80.23FF reserved FF80.2400 …FF80.2FFF Real-Time Clock – RTC 72423 FF80.3000 …FF80.31FF reserved FF80.3200 …FF80.33FF SCSI-Controller FF80.3400 …FF80.35FF...

  • Page 45: The Cpu 68030 Processor

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.2 The CPU 68030 Processor 3.2.1 Hardware The 68030 uses a nonmultiplexed address and data bus. Asynchronous Interface of the signals allow easy interfacing to the outside world; synchronous signals 68030 perform fast interaction.

  • Page 46: Vector Table Of The 68030

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description 3.2.3 Vector Table This table lists all vectors defined and used by the 68030 CPU. of the 68030 Table 12: Exception Vector Assignments Vector Number(s) Vector Offset (Hex) Assignment Reset Initial Interrupt Stack Pointer...

  • Page 47: The Floating Point Coprocessor (Fpcp)

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.3 The Floating Point Coprocessor (FPCP) The CPU board contains a Floating Point Coprocessor (FPCP 68882). 3.3.1 Features of the - 8 floating point data registers supporting 80-bit extended precision 68882 of real data (64-bit mantissa, 15-bit exponent, and one sign bit)

  • Page 48: Interfacing To The 68882

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description 3.3.2 Interfacing to The 68882 is a non-DMA type coprocessor which uses a subset of the the 68882 general purpose coprocessor interface supported by the 68030. Features of the interface implemented in the 68882 are as follows: - Main processor and 68882 communicate via standard bus cycles.

  • Page 49: Addressing The 68882

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.3.3 Addressing the The 68882 is addressed via the function codes of the 68030 and a part of 68882 the address bus. This is done automatically within the opcodes generated by most 68030/68882 floating-point compilers and assemblers.

  • Page 50: The Local Bus

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description 3.4 The Local Bus 3.4.1 The FGA-002 The CPU board also contains the FGA-002 Gate Array with 24,000 gates Gate Array and 304 pins. The FGA-002 Gate Array controls the local bus and builds the interface to the VMEbus.

  • Page 51: Bank Selection Of Dram

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual Write cycles are handled differently. In the case of a long-word access aligned to a 4-byte boundary, the DRAM can be written immediately. The parity info generated by FGA-002 will be written additionally to the DRAM.

  • Page 52: Board Type With Memory Capacity

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description defined memory range can be write protected in coordination with the VMEbus Address Modifier codes. For example, in privileged mode the memory could be read and written, while in non-privileged mode the memory could only be read, or a non-privileged access could be prohibited altogether.

  • Page 53: Reading The Shared Ram Capacity

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.4.4 Reading the The amount of Shared RAM may be read via three input pins from Port B Shared RAM of PI/T #2. The table below summarizes the encoding of these three bits.
  • Page 54 SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description The first read cycle of such a burst usually requires 5 CPU clock cycles (200 nanoseconds at 25 MHz). Due to the optimized design of the memory control logic, each subsequent cycle only requires 1 CPU clock cycle (40 nanoseconds) to complete.

  • Page 55: The System Prom Area

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.5 The System PROM Area The first two read cycles after reset of the microprocessor are operand fetches of the Initial Interrupt Stack Pointer (ISP) and the Initial Program Counter (IPC). These operands are always fetched from addresses and 0000.0004...

  • Page 56: Programming The System Flash Memory

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description The encoding of these bits is shown in the table below. Function Write to System Flash Memory unprotected Write to System Flash Memory protected CAUTION: Writes to the System Flash Memory must always be performed with a 4-byte wide port size and must be aligned on 4-byte boundaries.

  • Page 57: Device Types For The System Flash Memory

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.5.5 Device Types The following device types or equivalent are used by the System Flash for the System Memory: Flash Memory Table 14: Device Types used for System Flash Memory Default Device Device Capacity...

  • Page 58: The Boot Prom

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description 3.6 The Boot PROM The CPU board contains one or two 32-pin PROMs which are used to boot up the processor and initialize register contents of the FGA-002 Gate Array. This program finishes in such a manner that the 68030 microprocessor appears to have booted from the System Flash Memory.

  • Page 59: Device Type Selection For Optional Boot Prom (Socket J28)

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.6.1.2 Device Type Selection for The optional Boot PROM socket supports the use of Optional Boot - Programmable 5V Flash devices PROM (Socket J28) - EPROM (OTP) - EEPROM This is controlled by switch SW5-2.

  • Page 60: Programming Flash Devices

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description 3.6.1.4 Programming Besides the communication sequence, a programming voltage Vpp of Flash Devices 12V must be applied to the default Boot PROM (socket J36). Vpp is generated by the CPU-30 R4 and is controlled by PI/T #2.

  • Page 61: Opt. Boot Prom Addresses (J28), Sw5-1=Off

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.6.2.2 Opt. Boot PROM Boot PROM access to default Boot PROM and optional Boot PROM Addresses (J28), (Boot PROM selection switch SW5-1 in position OFF) SW5-1=OFF Default Used Device Device Type Start Address...

  • Page 62: Summary Of The Boot Prom Area

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description 3.6.3 Summary of Not Allowed Access with Function Code the Boot Supported Port Size Byte PROM Area Maximum Capacity 1 Mbyte Default Access Time 200 ns Access Address FFE0.0000 - FFEF.FFFF No. of Devices to be Installed...

  • Page 63: The Local Sram Memory

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.7 The Local SRAM Memory The SRAM memory is dedicated to the on-board default SRAM and an optional SRAM. For the optional SRAM there are two 32-pin DIL socket positions available. The socket position J87 allows the usage of a 28-pin SRAM or a 32-pin SRAM with a high active chip select for pin 30.

  • Page 64: Used Devices For Sram Area

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description The following instruction is fully supported from the SRAM memory area: MOVE.X ($FFC0 000Y), D0 X = B = Byte 1 Byte X = W = Word 2 Bytes X = L = Long Word...

  • Page 65: Access Time Selection Of The Sram Area

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual NOTE: The setup parameters of FGA-002 are stored in the SRAM located in the lower half of the SRAM address space. If the optional SRAM is enabled, the setup parameters of the optional SRAM will be used.

  • Page 66: Summary Of The Sram Area

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description Backup from the battery is controlled by switch SW11-1 and SW11-3. Default SW11-1 SW11-3 Description Position Backup from battery disabled for RTC and SRAM Backup from battery enabled for RTC, but disabled for SRAM Backup from battery enabled for RTC and SRAM 3.7.5...

  • Page 67: The Real-Time Clock (Rtc) 72423

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.8 The Real-Time Clock (RTC) 72423 There is an RTC 72423 installed on the CPU board, containing its own crystal to maintain accurate time and date. A battery is provided on the CPU board to allow the RTC to run even under power-down conditions.

  • Page 68: Rtc Programming Example

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description 3.8.3 /***************************************** Programming read RTC 72423 and load to RAM Example 30-Oct-87 M.S. *****************************************/ setclock(sy) register struct SYRAM *sy; register struct rtc7242 *rtc = RTC2; register long count=100000l; rtc->dcontrol = 1; /* hold clock */ while(count--) if(rtc->dcontrol&0x02)

  • Page 69: Backup Power For The Rtc

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual rtc->fcontrol = 5; rtc->fcontrol = 4; /* 24-hour clock */ rtc->sec10reg = sy->_ssec[0]/10; rtc->sec1reg = sy->_ssec[0]%10; rtc->min10reg = (char)(sy->_smin/10); rtc->min1reg = (char)(sy->_smin%10); rtc->hou10reg = (char)(sy->_shrs/10); rtc->hou1reg = (char)(sy->_shrs%10); rtc->yr10reg = sy->_syrs[0]/10; rtc->yr1reg = sy->_syrs[0]%10;...

  • Page 70: Summary Of The Rtc

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description Backup from the battery is controlled by switch SW11-1 and SW11-3. Default SW11-1 SW11-3 Description Position Backup from battery disabled for RTC and SRAM Backup from battery enabled for RTC, but disabled for SRAM Backup from battery enabled for RTC and SRAM 3.8.5...

  • Page 71: The Duscc 68562

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.9 The DUSCC 68562 The Dual Universal Serial Communications Controller 68562 (DUSCC) is a single-chip MOS-LSI communications device that provides two independent, multiprotocol, full duplex receiver/transmitter channels in a single package. Each channel consists of a receiver, a transmitter, a 16-bit multifunction counter/timer, a digital phase locked loop (DPLL), a parity/CRC generator and checker, and associated control circuits.

  • Page 72: Address Map Of Duscc #1 Registers

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description 3.9.2 Address Map The following tables contain the complete register map of DUSCC #1. of DUSCC #1 The first table pertains only to registers for Port #4, the second table for Registers Port #1, and the third table for registers common to both Port #1 and Port #4.

  • Page 73: Table 18. Serial I/O Port #1 (Duscc #1) Register Address Map

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual Table 18: Serial I/O Port #1 (DUSCC #1) Register Address Map Port Base Address: $FF80 2020 Address Offset Reset Mode Label Description (HEX) (HEX) Value $FF802020 DUSCMR1 Channel Mode Reg 1 DUSCMR2 Channel Mode Reg 2...

  • Page 74: Address Map Of Duscc #2 Registers

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description 3.9.3 Address Map The following tables contain the complete register map of DUSCC #2. of DUSCC #2 The first table pertains only to registers for Port #2, the second table for Registers Port #3, and the third table for registers common to both Port #2 and Port #3.

  • Page 75: Table 21. Serial I/O Port #3 (Duscc #2) Register Address Map

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual Table 21: Serial I/O Port #3 (DUSCC #2) Register Address Map Port Base Address: $FF80 2220 Address Offset Reset Mode Label Description (HEX) (HEX) Value $FF802220 DUSCMR1 Channel Mode Reg 1 DUSCMR2 Channel Mode Reg 2...

  • Page 76: Configuration Of Serial I/O Ports

    RS-232 and In order to conserve board space and to simplify varying the serial RS-422/485 interfaces, FORCE Computers has developed RS-232 and RS-422/485 Driver Modules hybrid modules: the FH-002 and FH-003. These 21-pin single in-line (SIL) modules are installed in sockets so that they may be easily changed to meet specific application needs.
  • Page 77 Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual The serial ports may be configured for RS-232 or RS-422/485. SW12-1 Description OFF (default) RS-232 support for port #1 FH-002 hybrid must be installed for J118 RS-422/485 support for port #1 FH-003 hybrid must be installed for J118...
  • Page 78 SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description When serial port #4 is configured for RS-232 operation, its I/O signals will be connected to the VME P2 connector as follows: Signal Input Description Output Connector P2 Data Carrier Detect Receive Data...

  • Page 79: Rs-422/Rs-485 Hardware Configuration Of Serial Ports

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.9.7 RS-422/RS-485 It is possible to configure any or all of the four serial ports to be RS-422 Hardware compatible or – as factory option – RS-485 compatible. By default, all Configuration four serial ports are configured for RS-232 operation. For proper RS-...

  • Page 80: Termination Resistors For Rs-422/Rs-485 Configuration

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description When the serial ports #1, #2 and #3 are configured for RS-422 operation, its I/O signals will be connected to the optional 5-row VME P2 connector as follows: Port Signal Input Output Connector P2...

  • Page 81: Summary Of Duscc #2

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.9.10 Summary of Device 68562 DUSCC DUSCC #2 Access Address FF80.2200 Port Width Byte Interrupt Request Level Software programmable FGA-002 Interrupt Channel Local IRQ #5 3.10 The PI/T 68230 The MC68230 Parallel Interface/Timer provides versatile double buffered parallel interfaces and an operating system oriented timer.

  • Page 82: Address Map Of The Pi/T #1 Registers

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description 3.10.2 Address Map PI/T #1 is accessible via the 8-bit local I/O bus (byte mode). The of the PI/T #1 following table shows the register layout of the PI/T #1. Registers Table 24: PI/T #1 Register Layout...

  • Page 83: Rotary Switches At Pi/T #1

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual Table 25: PI/T #1 Interface Signals (Continued) Function In/Out User I/O via optional B5 or optional 5-row VME P2 connector " " " Floppy Disk Drive Control " " " " " DMA Controller Control "...

  • Page 84: Floppy Disk Drive Control Lines At Pi/T #1

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description Table 26: Rotary Switch Signals Assignment (Continued) Port A Bit Switch "2" NOTE: The rotary switches serve a special function in conjunction with the RESET and ABORT switches. This functionality is built into the Boot EPROM and is described in detail in the Boot Software description of the FGA-002 User’s Manual.

  • Page 85: Dma Control Lines At Pi/T #1

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.10.6 DMA Control PB6, PB7: Lines at PI/T #1 These lines control the local peripheral bus when the DMA controller is active. The signal PC6 controls the direction of the DMA transfer (read vs.

  • Page 86: Interrupt Request Signals Of Pi/T #1

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description 3.10.8 Interrupt TOUT: Request Signals The PI/T #1 pin PC3 is used as an interrupt request output. The 24-bit of PI/T #1 timer can generate interrupt requests at a software programmable level. This interrupt request line is connected to the IRQ #2 of the FGA-002.

  • Page 87: Summary Of Pi/T #1

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.10.11 Summary of Device 68230 PI/T PI/T #1 Access Address FF80.0C00 Port Width Byte Interrupt Request Level Software programmable FGA-002 Interrupt Channel (Timer IRQ) Local IRQ #2 3.10.12 Address Map The PI/T2 is accessible via the 8-bit local I/O bus (byte mode). The of the PI/T #2 following table shows the register layout of PI/T2.

  • Page 88: 12-Bit User I/O Port At Pi/T #2

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description Table 28: PI/T #2 Interface Signals Function In/Out User I/O via optional B6 or optional 5-row VME P2 connector " " " " " " " User I/O via optional B6 or optional 5-row VME P2 connector "...

  • Page 89: Memory Size Identification At Pi/T #2

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual PI/T #2 Connection B6 VME-P2 The connector B6 (factory option) provides, besides the 12-bit user port signals, power signals. The +5V power on pin 1 and pin 16 is protected by a non destroyable 1A-fuse. The GND power is connected at pin 8 and pin 9.

  • Page 90: Interrupt Request Signal Of Pi/T #2

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description 3.10.17 Interrupt TOUT: Request Signal PI/T #2 pin PC3 is used as a Timer Interrupt Request output. The 24-bit of PI/T #2 timer can generate interrupt requests at a software programmable interval. The Timer Interrupt Request line is connected to the local IRQ #3 of the FGA-002.

  • Page 91: Floppy Drive Write Protect Signal At Pi/T #2

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual CAUTION: PI/T #2 pin PC2 must be programmed as an input. Function Write to Boot PROM unprotected Write to Boot PROM protected 3.10.20 Floppy Drive PC4: Write Protect From this line the status of the write protection for the System Flash Signal at PI/T #2 Memory may be monitored.

  • Page 92: Reserved Lines At Pi/T #2

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description CAUTION: PI/T #2 pin PC6 must be programmed as an output. Function Vpp on Vpp off The Vpp generator is shared between the System Flash Memory and the default Boot PROM socket. SEE ALSO: For further information please refer to Section 3.5, ‘The System PROM Area,’...

  • Page 93: Scsibus Controller Mb 87033/34

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.11 SCSIbus Controller MB 87033/34 The MB 87033/34 SCSI Controller, with its up to 4 Mbytes/s data transfer rate, is installed on the CPU to interface directly to SCSI Winchester disks, optical drives or tape streamers.

  • Page 94: 1Dma Control Lines

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description The DMA Controller includes a 32-byte FIFO which waits until the 32 bytes are filled and then requests local bus mastership for an eight cycle data transfer (32 bit in parallel). In addition to the 32-byte DMA FIFO, the DMA channel includes a second FIFO (8 bytes deep) to fill the DMA FIFO if the DMA transfer to main memory is taking place.

  • Page 95: 2Dma Transfer Programming Example

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.11.3.2DMA Transfer *--------------------------------------------------------------- Programming * DATA OUTPUT TO SCSI TARGET, USING THE MB87033/34 AND THE Example * FGA-002 DMA CHANNEL *--------------------------------------------------------------- BCLR #$07,PBDR+PI_T ;SELECT DMA WORKS WITH SCSI BCLR #$06,PBDR+PI_T ;SELECT TRANSFER DMA TO SCSI * THE FOLLOWING AUX VALUES ARE ONLY VALID FOR THE CPU-30 ! MOVE.B...

  • Page 96: 2Scsibus Signal Termination

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description Information transfers on the data bus are asynchronous and follow a defined REQ/ACK handshake protocol. One byte of information may be transferred with each handshake. An option is defined for synchronous data transfer.

  • Page 97: The Floppy Disk Controller

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.12 The Floppy Disk Controller The CPU board contains a single chip floppy controller, the FDC37C65C. The FDC is connected to the DMA controller of the FGA-002 Gate Array. The installed driver/receiver circuits allow direct connection of 3 1/2"...

  • Page 98: Drive Select Support

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description 3.12.4 Drive Select The CPU-30 R4 supports two drive selects - DSEL 1 and DSEL 2 which Support are generated by the FDC37C65C-Controller. 3.12.5 Motor-On The FDC37C65C Floppy Controller provides two signals for motor Support control.

  • Page 99: 1Dma Transfer Programming Example

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual Signal VME P2 Connector WPROT TRU00 WGATE WDATA STEPX DIRBC MOTOR DSEL1 C5, (C7) DSEL2 C6, (C3) INDEX HLOAD (EJECT) 1. Backward compatibility to DSEL3 2. backward compatibility to DSEL4 3. factory option NOTE: For the connection to the IOBP-1 back panel, please refer to Section 2.11, ‘The SYS68K/IOBP-1,’...

  • Page 100: Jumper Setting On The Floppy Disk Drive

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description 3.12.8 Jumper Setting on the Floppy Disk Drive CAUTION: If the floppy disk drive contains a jumper which connects the floppy disk drive frame electrically with DC ground, insertion of this jumper is not allowed and can cause damage.

  • Page 101: The Local Area Network Interface

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.13 The Local Area Network Interface The CPU board offers a Local Area Network (LAN) interface. The LAN interface consists of an Am7990 LANCE (Local Area Network Controller for Ethernet), an Am7992 SIA (Serial Interface Adapter), two 32-Kbyte static RAMs, and control logic.

  • Page 102: The Am7990 Lance

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description The figure below shows a simplified functional block diagram of the Ethernet Interface. Figure 5: Functional Block Diagram of the Ethernet Interface SRAM Am7990 Am79928 LANCE TRANSFORMER LOCAL BUS LANCE BUS 3.13.2 The Am7990...

  • Page 103: 2The Lance Interrupt

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.13.2.2The LANCE The LANCE is able to interrupt the CPU on a programmable level. It is Interrupt connected to the Interrupt Request Channel 6 (IRQ #6) of the FGA-002 Gate Array. Like all on-board interrupts, the interrupt priority level of the LANCE may be selected by programming the FGA-002.

  • Page 104: 2The Am7992B Receiver

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description 3.13.4.2The Am7992B The receiver has the responsibility of signalling to the LANCE when Receiver there is a message to receive. It decodes the Manchester-encoded data stream from the Ethernet cable and sends the data to the LANCE.

  • Page 105: Function Switches And Indication Leds

    "DOWN" position. In addition, a local timer guarantees a minimum reset time of 200-300ms. Power fail and power up also force a reset (200-300ms) to start the board if the supply voltage is out of range (below approximately 4.7 Volts).

  • Page 106: Bm" Led

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description 3.14.4 "BM" LED If the CPU board is the current VMEbus master, the green BM LED is lit. This provides the user with a convenient visual indication of the status of the VMEbus.

  • Page 107: The Cpu Board Interrupt Structure

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.15 The CPU Board Interrupt Structure The FGA-002 Gate Array on the CPU board monitors all local and VMEbus interrupts. Each interrupt request from the local bus (SCSI and floppy disk controllers DUSCCs, RTC, PI/T timers, etc) as well as the FGA-002 specific interrupt requests are combined with seven VMEbus interrupt requests.

  • Page 108: Vmebus Interface

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description 3.16 VMEbus Interface The CPU board contains a complete VMEbus interface which is compatible with the IEEE 1014 standard (VMEbus Revision C). The VMEbus interface supports 8, 16, 32 bit, and unaligned data transfers.

  • Page 109: Vmebus Master Interface

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.17 VMEbus Master Interface 3.17.1 Data Transfer The memory map of the CPU board divides the 4-Gbyte address space of Size of the the 68030 microprocessor into areas of local memory, local I/O, VMEbus FGA-002 internal registers, and VMEbus space.

  • Page 110: Address Modifier Implementation

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description This default configuration is useful if a user program or an operating system is started, and additional memory boards with known data sizes are installed. SEE ALSO: For details on the usage of the rotary switches, please refer to Section 5.4.3, ‘Control Switches (Rotary Switches),’...

  • Page 111: Table 34. Address Modifier Codes

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual All allowed and defined Address Modifier (AM) Codes are listed in the next table. Those codes that are supported by the CPU board are marked with an asterisk (*). The 4-Gbyte address range of the microprocessor is split into several areas to support all of the listed AM codes.

  • Page 112: Table 35. Address Modifier Codes Used By The Cpu Board

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description Table 34: Address Modifier Codes (Continued) Address Modifier Code Function User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined User Defined...
  • Page 113 Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual Table 35: Address Modifier Codes Used by the CPU Board Addresses Range Code 543210 FA00.0000 FORCE Message 001101 Broadcast Range 001001 FAFF.FFFF FBFF.0000 VMEbus (Standard Access) 111110 A24: D32, D24, D16, D8 111101 111010 FBFE.FFFF...

  • Page 114: Vmebus Slave Interface

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description 3.18 VMEbus Slave Interface 3.18.1 The Access The on-board shared RAM of the CPU board is also accessible from the Address VMEbus by another VMEbus master. Both the beginning and ending address of the Shared RAM are programmable in 4-Kbyte increments inside the FGA-002.

  • Page 115: The Vmebus Interrupt Handler

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.19 The VMEbus Interrupt Handler All seven VMEbus interrupt request (IRQ) signals are connected to the interrupt handling logic on the FGA-002 Gate Array. Each of the VMEbus IRQ signals can be separately enabled or disabled. The FGA-002 Gate Array allows high-end multiprocessor environment board usage with distributed interrupt handling.

  • Page 116: Vmebus Arbitration

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description 3.20 VMEbus Arbitration Each transfer to/from an off-board address causes a VMEbus access cycle. The VMEbus defines an arbitration mechanism to arbitrate for bus mastership. The CPU board includes a VMEbus requester, so that it may access external VMEbus resources, and a VMEbus arbiter, so that it may optionally act as "Slot-1"...

  • Page 117: Vmebus Release Modes

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.20.3 VMEbus The CPU board contains several different software-selectable VMEbus Release Modes release functions to relinquish VMEbus mastership. The bus release operation is independent of whether or not the on-board VMEbus arbiter is enabled and independent of the VMEbus request level. Easy handling and usage of the bus release functions is provided through the FGA-002 Gate Array.

  • Page 118: 4Release On Bus Clear (Rbclr)

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description the bus is approximately equal to the programmed ROR delay time (see above) plus 100 microseconds. This function cannot be disabled. The timer is only effective for CPU cycles to the VMEbus and not for cycles initiated by the on-board DMA controller.

  • Page 119: 7Summary Of Release Modes

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.20.3.7Summary of Table 37: Bus Release Functions Release Modes Function Enabled VME is Released Every Cycle Always Always RBCLR BRx* Active or after Timeout Always Always RBCLR BRx* Active or after Timeout or BCLR* Active...

  • Page 120: Slot-1 Detection

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description 3.21 Slot-1 Detection The CPU-30 R4 may be used as System Controller when plugged into slot-1. When the board is a slot-1 device, the hardware of the CPU-30 R4 setups the required system controller functions. These are:...

  • Page 121: Slot-1 Status Register

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual (incorrectly) not driving its Bus Grant Out Level 3 (BG3OUT) on VME to the high signal level as defined by the VME specification. In this case the CPU-30 R4 will probe its Bus Grant In Level 3 at a low signal level and conclude that slot-1 is detected.

  • Page 122: The Sysclk Driver

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description 3.21.4 The SYSCLK The CPU board contains all the necessary circuitry to support the Driver SYSCLK signal. The output signal is a stable 16 MHz signal with a 50% duty cycle. The driver circuitry for the SYSCLK signal has a current driver capacity of 64mA.

  • Page 123: Exception Signals

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.22 Exception Signals VMEbus specification includes signals SYSFAIL*, SYSRESET* and ACFAIL* for signaling exceptions or status. The SYSFAIL*, SYSRESET* and ACFAIL* signals are connected to the CPU board through buffers, switches and the FGA-002 Gate Array.

  • Page 124: The Acfail* Signal

    The ACFAIL* line is ignored by VMEPROM firmware. The VMEbus Signal requester logic in the FGA-002 monitors the ACFAIL* signal and may force a release of VMEbus mastership when it is asserted. The CPU board can never drive the ACFAIL* signal. Page 111...

  • Page 125: Reset Generation

    Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual 3.23 Reset Generation There is an IEEE 1014 compatible SYSRESET* driver installed on the CPU board. The reset generation circuitry operates when the power supply voltage Vcc reaches approximately 3 volts. The local reset signal...

  • Page 126: Voltage Sensor Unit

    SYS68K/CPU-30 R4 Technical Reference Manual Hardware Description 3.23.3 Voltage Sensor The voltage sensor unit serves as a reset generator. Power up reset is Unit provided by this sensor, as soon as the supply voltage Vcc has reached approximately 3 volts. The local reset signal will be asserted if Vcc subsequently falls below 4.7 volts.
  • Page 127 Hardware Description SYS68K/CPU-30 R4 Technical Reference Manual Page 114...

  • Page 128: Circuit Schematics And Data Sheets

    Set of Data Sheets 4 Circuit Schematics and Data Sheets 4.1 Circuit Schematics of SYS68K/CPU-30 R4 Copies of the CPU-30 R4 schematics are found on the next page. The schematics contain the signal and unit cross references as well as the history of the schematics.

  • Page 129: List Of Data Sheets

    Set of Data Sheets SYS68K/CPU-30 R4 Technical Reference Manual 4.2 List of Data Sheets This is a list of the data sheets which are relevant to the SPARC CPU-30 R4. Copies of these data sheets are found on the following pages.

  • Page 130: Rtc 72421

    SYS68K/CPU-30 R4 Technical Reference Manual Set of Data Sheets 4.2.1 RTC 72421 Page 117...

  • Page 131: Duscc 68562

    Set of Data Sheets SYS68K/CPU-30 R4 Technical Reference Manual 4.2.2 DUSCC 68562 Page 118...

  • Page 132: Pi/T Ts68230

    SYS68K/CPU-30 R4 Technical Reference Manual Set of Data Sheets 4.2.3 PI/T TS68230 Page 119...

  • Page 133: Scsi 87033/34

    Set of Data Sheets SYS68K/CPU-30 R4 Technical Reference Manual 4.2.4 SCSI 87033/34 Page 120...

  • Page 134: Fdc37C65C

    SYS68K/CPU-30 R4 Technical Reference Manual Set of Data Sheets 4.2.5 FDC37C65C Page 121...

  • Page 135: Lance Am79C90

    Set of Data Sheets SYS68K/CPU-30 R4 Technical Reference Manual 4.2.6 LANCE Am79C90 Page 122...

  • Page 136: Sia Am7992B

    SYS68K/CPU-30 R4 Technical Reference Manual Set of Data Sheets 4.2.7 SIA Am7992B Page 123...

  • Page 137: Motorola Mc68030 And Mc68882

    Set of Data Sheets SYS68K/CPU-30 R4 Technical Reference Manual 4.2.8 Motorola MC68030 and MC68882 Page 124...

  • Page 138: Vmeprom

    SYS68K/CPU-30 R4 Technical Reference Manual VMEPROM 5 VMEPROM 5.1 General Information This CPU board operates under the control of VMEPROM, a ROM resident real-time multiuser multitasking monitor program. VMEPROM provides the user with a debugging tool for single and multitasking real- time applications.

  • Page 139: Power-Up Sequence

    VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual 5.3 Power-up Sequence After power up, the processor retrieves the initial stack pointer and program counter from address locations 0 and 4 . These locations are the first 8 bytes of the Boot ROM area. They are mapped down to address for a defined start after reset or power up.

  • Page 140: Front Panel Switches

    SYS68K/CPU-30 R4 Technical Reference Manual VMEPROM 5.4 Front Panel Switches 5.4.1 RESET Switch Pressing the RESET switch on the front panel causes all programs to terminate immediately and resets the processor and all I/O devices. When the VMEPROM kernel is started, it overwrites the first word in the user memory after the task control block with an EXIT system call.

  • Page 141: Table 38. Upper Rotary Switch (Sw2)

    VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual The following describes the software definition for the rotary switches: Table 38: Upper Rotary Switch (SW2) Bit 3: This bit indicates whether the RAM disk should be initialized after reset. If this bit is set to "0" (settings 0-7), the RAM disk is initialized as defined by bit 0 and 1.

  • Page 142: Table 41. Program After Reset

    SYS68K/CPU-30 R4 Technical Reference Manual VMEPROM Table 41: Program After Reset Bit 3 Bit 2 Lower Switch (SW 1) selected on VMEPROM C,D,E,F USER PROGRAM AT 4070.0000 8,9,A,B AUTOBOOT SYSTEM 4,5,6,7 USER PROGRAM AT 4080.0000 0,1,2,3 Table 42: Boot an Operating System (if AUTOBOOT is...

  • Page 143: Default Memory Usage Of Vmeprom

    VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual 5.4.4 Default By default, VMEPROM uses the following memory assignment for the Memory Usage CPU board: of VMEPROM Table 44: Main Memory Layout Start Address End Address Type 0000.0000 0000.03FF Vector Table 0000.0400 0000.0FFF System Configuration Data 0000.1000...
  • Page 144 SYS68K/CPU-30 R4 Technical Reference Manual VMEPROM Table 45: Layout of System Flash Memory (Continued) (Pointer to Shell) ..VMEPROM Shell, System Tools, Debugging Tools, Line Assembler/ Disassembler FF03.6000 FF03.CFFF UNIX V.3 / PDOS Boot Program FF03.D000 FF03.FFFF reserved FF04.0000 FF07.FFFF Flash Programming Utility FF08.0000...
  • Page 145 VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual Page 132...

  • Page 146: Devices And Interrupts Used By Vmeprom

    SYS68K/CPU-30 R4 Technical Reference Manual VMEPROM 6 Devices and Interrupts used by VMEPROM 6.1 Addresses of the On-board I/O Devices The following table shows the on-board I/O devices and their addresses: Table 46: On-board I/O Devices Base Address Device FF80.0C00 PI/T1 68230 FF80.0E00...

  • Page 147: Off-Board Interrupt Sources

    VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual 6.3 Off-board Interrupt Sources VMEPROM supports several VMEbus boards. As these boards are interrupt driven, the level and vectors must be defined for VMEPROM to work properly. The following table shows the default setup of the interrupt levels and vectors of the supported hardware.

  • Page 148: Concept Of Vmeprom

    SYS68K/CPU-30 R4 Technical Reference Manual VMEPROM 7 Concept of VMEPROM 7.1 Getting Started After power up or after RESET has been pressed, VMEPROM prints a banner showing the version and revision being used and prints the prompt ("?"). If the above message does not appear, check the following: 1.

  • Page 149: Vmeprom Commands

    VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual 7.3 VMEPROM Commands VMEPROM supports many commands. All of these commands are resident and are available at any time. Most of these commands are common for all versions of VMEPROM. All the common commands of VMEPROM are described in detail in the VMEPROM User's Manual.

  • Page 150: Special Vmeprom Commands For Cpu Boards

    SYS68K/CPU-30 R4 Technical Reference Manual VMEPROM 8 Special VMEPROM Commands for CPU Boards The following commands are implemented on the CPU board in addition to those listed in the VMEPROM User's Manual. 8.1 ARB - Set the Arbiter of the CPU Board...

  • Page 151: Config - Search Vmebus For Hardware

    VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual 8.2 CONFIG - Search VMEbus for Hardware Format: CONFIG This command searches the VMEbus for available hardware. It is useful if VMEPROM is started and bit 0 of the lower rotary switch on the front panel is set to "1", so that VMEPROM does not check the configuration...

  • Page 152: Ferase - Erase Flash Memories

    SYS68K/CPU-30 R4 Technical Reference Manual VMEPROM 8.3 FERASE - Erase Flash Memories Format: FERASE <flashbank> FERASE <flashbank>,<flashoffset>,<length> The FERASE command allows erasing Flash Memory banks. The first format of the command erases the whole Flash Memory bank. The second format allows specifying a region to erase.

  • Page 153: Fga - Change Boot Setup For Gate Array

    VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual 8.4 FGA - Change Boot Setup for Gate Array Format: FGA Some registers of the gate array are definable by the user. The contents of these registers is stored in the on-board battery SRAM in a short form.

  • Page 154: Flush - Set Buffered Write Mode

    SYS68K/CPU-30 R4 Technical Reference Manual VMEPROM 8.5 FLUSH - Set Buffered Write Mode Format: FLUSH FLUSH ? FLUSH ON FLUSH OFF This command flushes all modified hashing buffers for disk write or enable/disable buffered write mode for the local SCSI controller.

  • Page 155: Fmb - Force Message Broadcast

    VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual 8.6 FMB - FORCE Message Broadcast Format: FMB <slotlist>,<FMB channel>,<message> FMB [<FMB channel>] The FMB command allows sending a byte message to individual slots in the backplane, broadcast to all the boards, and getting a pending message.

  • Page 156: Fprog - Program Flash Memories

    SYS68K/CPU-30 R4 Technical Reference Manual VMEPROM 8.7 FPROG - Program Flash Memories Format: FPROG <flashbank>,<source> FPROG <flashbank>,<source>,<flashoffset> FPROG <flashbank>,<source>,<flashoffset>,<length> The FPROG command allows programming Flash Memory banks. If the flash memory is not empty, it must be erased before reprogramming it (see section 8.3 “FERASE - Erase Flash Memories” on page 139).

  • Page 157: Functional - Perform Functional Test

    VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual 8.8 FUNCTIONAL - Perform Functional Test Format: FUNCTIONAL NOTE: This command is not designed for the user, but instead for internal purposes by FORCE COMPUTERS. 8.9 MEM - Set Data Bus Width of the VMEbus...

  • Page 158: Selftest - Perform On-Board Selftest

    SYS68K/CPU-30 R4 Technical Reference Manual VMEPROM 8.10 SELFTEST - Perform On-board Selftest Format: SELFTEST This command performs a test of the on-board functions of the CPU board. It may only run if no other tasks are created. If there are any other tasks, no selftest will be made and an error will be reported.

  • Page 159: Installing A New Hard Disk

    VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual 8.11 Installing a New Hard Disk The FRMT command of VMEPROM may be used to set all hard disk parameters, to format the Winchester and to divide the disk into logical partitions. Before starting the FRMT command, the number of the last logical block of the Winchester must be known.
  • Page 160 SYS68K/CPU-30 R4 Technical Reference Manual VMEPROM Current Winch Drive 0 Parameters: # of Heads = 10 # of Cylinders = 1022 Physical Blocks per Track = 32 Physical Bytes per Block = 256 Shipping Cylinder = 0 Step rate = 0...
  • Page 161 VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual Disk # Logical Trks Physical Trks PDOS sectors Base,Top Base,Top Total/{boot} 0,1502 0,1502 48064/47872 1503,3005 1503,3005 48064/47872 3006,4508 3006,4508 48064/47872 4509,6011 4509,6011 48064/47872 6012,7514 6012,7514 48064/47872 7515,9017 7515,9017 48064/47872 9018,9097 9018,9097 2528/2336 9098,9177 9098,9177...

  • Page 162: Appendix To Vmeprom

    FORCE WFC-1 ADDR: $FF00D100 9.1.1 VMEbus In general, every FORCE memory board can be used together with Memory VMEPROM. The base address must be set correctly in order to use the board within the tasking memory of VMEPROM. That is, the board base addresses of any additional memory boards must be set to be contiguous to the on-board memory.
  • Page 163 Appendix to VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual Please refer to the SIO User's Manual for setup. If a second SIO-1/2 board will be used, the base address must be set to FCB0.0200 . The AM-decoder setup described above must again be used. Please refer to the SIO User's Manual for the address setup of the second SIO board.

  • Page 164: Sys68K/Isio-1/2

    SYS68K/CPU-30 R4 Technical Reference Manual Appendix to VMEPROM SIO-1 FCB0.0000 ISIO-1 FC96.0000 9.1.3 SYS68K/ISIO-1/2 These serial I/O boards are set to the address 96.0000 in the standard VME address range by default. VMEPROM awaits this board at this address (FC96.0000 for the CPU-30 R4);...

  • Page 165: Sys68K/Wfc-1 Disk Controller

    Appendix to VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual VMEPROM supports two serial I/O boards. These can be the SIO-1/2 or ISIO-1/2 board or a mixture of both. The first board of each type must be set to the first base address. When using one SIO-1 and one ISIO-1 board,...

  • Page 166: Sys68K/Iscsi-1 Disk Controller

    SYS68K/CPU-30 R4 Technical Reference Manual Appendix to VMEPROM 9.1.5 SYS68K/ISCSI-1 VMEPROM supports up to two floppy disk drives and three Winchester Disk Controller disk drives together with the ISCSI-1 disk controller. The floppy drives must be jumpered to drive select 3 and 4 and can be accessed as disk number 0 and 1 out of VMEPROM.

  • Page 167: S-Record Formats

    Appendix to VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual If this setup is done once for a particular drive, the data is stored in the first sector of the Winchester and is loaded automatically when the disk controller is installed in VMEPROM. Upon viewing the VMEPROM Banner, the driver for the local SCSI controller is already installed.
  • Page 168 SYS68K/CPU-30 R4 Technical Reference Manual Appendix to VMEPROM Example: S214020000000004440002014660000CB241F8044CB1 S214020010203C0000020E428110C1538066FA487AE4 S214020020001021DF0008487A001221DF000C4E750E S21402003021FC425553200030600821FC41444452C2 Check-sum XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX--- Data 0200XX----------------------------------- 24-bit Address 14----------------------------------------- Byte Count S2------------------------------------------- Record Type S9030000FC FC----------------------------------- Check-sum 0000------------------------------------- Data 03----------------------------------------- Byte Count S9------------------------------------------- Record Type Page 155...

  • Page 169: System Ram Definitions

    Appendix to VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual 9.3 System RAM Definitions /* SYRAM:H -- DEFINITION OF SYRAM BLOCK OF MEMORY 05-Jan-88 Revised to correspond to PDOS 3.3 BRIAN C. COOPER, EYRING RESEARCH INSTITUTE, INC. Copyright 1985-1988 #define /* number of tasks #define ((NT+3)&0xFC)
  • Page 170 SYS68K/CPU-30 R4 Technical Reference Manual Appendix to VMEPROM /*014*/ char *_sram; /* run module B$SRAM /*018*/ int spare1; /* reserved for expansion /*01A*/ int _fcnt; /* fine counter /*01C*/ long _tics; /* 32 bit counter /*020*/ unsigned char _smon; /* month /*021*/ unsigned char _sday;...
  • Page 171 Appendix to VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual the following change with different configurations: configuration for VMEPROM is defined to: NT = 64, NF = 64, MZ = $400000 NOTE: the offset on top of each line is calculated only for this configuration /*019C*/ char _maps[NMB];...

  • Page 172: Task Control Block Definitions

    SYS68K/CPU-30 R4 Technical Reference Manual Appendix to VMEPROM 9.4 Task Control Block Definitions #define MAXARG /* max argument count of the cmd line #define MAXBP /* max 10 breakpoints #define MAXNAME /* max 5 names in name buffer #define TMAX...
  • Page 173 Appendix to VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual /*40A*/ long _trc; /* trace vector /*40E*/ long _fpa[2]; /* floating point accumulator /*416*/ long *_fpe; /* fp error processor address /*41A*/ char *_clp; /* command line pointer /*41E*/ char *_bum; /* beginning of user memory /*422*/ char *_eum;...
  • Page 174 SYS68K/CPU-30 R4 Technical Reference Manual Appendix to VMEPROM /*654*/ WORD bpocc[MAXBP]; /* # of times the breakpoint should be /* skipped /*668*/ WORD bpcocc[MAXBP]; /* # of times the breakpoint is already /* skipped /*67C*/ LWORD bptadr; /* temp. breakpoint address /*680*/ WORD bptinst;...

  • Page 175: Interrupt Vector Table Of Vmeprom

    Appendix to VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual 9.5 Interrupt Vector Table of VMEPROM Vector Number Vector Address Assignment 0 (00 Reset: Initial Supervisor Stack Pointer 1 (01 Reset: Initial Program Counter 2 (02 Bus Error 3 (03 Address Error...
  • Page 176 SYS68K/CPU-30 R4 Technical Reference Manual Appendix to VMEPROM Vector Number Vector Address Assignment 53 (35 FP Overflow 54 (36 FP Signaling NAN 55 (37 (Unassigned, Reserved) 56 (38 PMMU Configuration 57 (39 PMMU Illegal Operation 58 (3A PMMU Access Level Violation...
  • Page 177 Appendix to VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual Vector Number Vector Address Assignment 236 (EC DMA Normal 237 (ED PARITY Error 238 (EE Reserved 239 (EF Reserved 240 (F0 LOCAL1 241 (F1 LOCAL2 242 (F2 LOCAL3 243 (F3 LOCAL4 244 (F4...

  • Page 178: Benchmark Source Code

    Appendix to VMEPROM 9.6 Benchmark Source Code *************************************************************** ** Module name: Assembler benchmarks Version: 1.0 ** date started: 20-Apr-87 M.S. last update: 23-Apr-87 M.S. ** Copyright (c) 1986/87 FORCE Computers GmbH Munich *************************************************************** section 0 alt,P=68020,P=68881 xdef .benchex xdef .BEN1BEG,.BEN1END xdef .BEN2BEG,.BEN2END...
  • Page 179 Appendix to VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual * BENCH #3: SUBSTRING CHARACTER SEARCH 100.000 TIMES TAKEN FROM EDN 08/08/85 MOVE.L #100000,D4 @002 MOVE.L #15,D0 MOVE.L #120,D1 LEA.L EDN1DAT(PC),A1 LEA.L EDN1DAT1(PC),A0 BSR.S EDN1 SUBQ.L #1,D4 BNE.S @002 ****** BEGIN EDN BENCH #1 ******* EDN1 MOVEM.L D3/D4/A2/A3,-(A7)
  • Page 180 SYS68K/CPU-30 R4 Technical Reference Manual Appendix to VMEPROM MOVEQ.L #10,D1 BSR.S EDN2 MOVEQ.L #1,D0 MOVEQ.L #11,D1 BSR.S EDN2 MOVEQ.L #1,D0 MOVE.W #123,D1 BSR.S EDN2 MOVEQ.L #3,D0 ; RESET MOVEQ.L #10,D1 BSR.S EDN2 MOVEQ.L #1,D0 MOVEQ.L #11,D1 BSR.S EDN2 MOVEQ.L #1,D0 MOVE.W...
  • Page 181 Appendix to VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual EDN3 MOVEM.L D1-D7,-(A7) MOVE.L D1,D2 MOVE.W D0,D7 SUBQ.W #2,D7 @010 ADDQ.L #1,D1 MOVE.L D1,D3 ADD.L D0,D2 MOVE.L D2,D4 @020 BFEXTU (A0){D3:1},D5 BFEXTU (A0){D4:1},D6 BFINS D5,(A0){D4:1} BFINS D6,(A0){D3:1} ADD.L D0,D3 ADDQ.L #1,D4 CMP.L D3,D4 BNE.S...
  • Page 182 SYS68K/CPU-30 R4 Technical Reference Manual Appendix to VMEPROM * BENCH #8: FLOATING POINT 1.000.000 SINUS MOVE.L #1000000,D5 FMOVE.L #1,FP1 @010 FSIN.X SUBQ.L #1,D5 BNE.S @010 PAGE * BENCH #9: FLOATING POINT 1.000.000 MULTIPLICATIONS MOVE.L #1000000,D5 FMOVE.L #1,FP0 FMOVE.L #1,FP1 @010 FMUL.X...
  • Page 183 Appendix to VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual * PDOS BENCHMARK #4: SEND TASK MESSAGE CLR.L ;SELECT TASK #0 LEA.L MES01(PC),A1 ;POINT TO MESSAGE MOVE.L #100000,D6 @000 XSTM ;SEND MESSAGE XKTM ;READ MESSAGE BACK SUBQ.L #1,D6 ;DONE? BGT.S @000 MES01 DC.B...

  • Page 184: Modifying Special Locations In Rom

    SYS68K/CPU-30 R4 Technical Reference Manual Appendix to VMEPROM 9.7 Modifying Special Locations in ROM The following table describes some special locations in the VMEPROM binary image. These locations define the default setup of the name of the start-up file, user program location and RAM disk addresses. These options can be selected by front panel switches.

  • Page 185: Table 49. User's Patch Table

    Appendix to VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual The address of the following table is located at offset 000C relative to the beginning of the VMEPROM image: Table 49: User’s Patch Table Offset Size Default Description DS.B 'SY$STRT',0 Name of the start-up file. It has to be a 0-terminated string.
  • Page 186 SYS68K/CPU-30 R4 Technical Reference Manual Appendix to VMEPROM Example of how to find this table: ? M FF00000C L FE00000C FE00E000 : . ? MD FE00E000 70 FF00E000: 53 59 24 53 54 52 54 00 00 00 00 00 00 00 00 00 SY$STRT..

  • Page 187: Binding Applications To Vmeprom

    Appendix to VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual 9.8 Binding Applications to VMEPROM 9.8.1 General In general, there are two ways to bind an application program in Flash Information Memory to the VMEPROM kernel. In all cases the application program is executed in user mode.
  • Page 188 SYS68K/CPU-30 R4 Technical Reference Manual Appendix to VMEPROM SEE ALSO: For further information please refer to Table 45, “Layout of System Flash Memory,” on page 130. Now the modified image can be programmed into System Flash as described in Section 9.7, ‘Modifying Special Locations in ROM,’ on page 171.
  • Page 189 Appendix to VMEPROM SYS68K/CPU-30 R4 Technical Reference Manual Page 176...

  • Page 190: Special Fga Boot Commands

    SYS68K/CPU-30 R4 Technical Reference Manual FGA Boot Software 10 Special FGA Boot Commands The booter on this CPU board is the FGA-002 Boot Software. At first FGA Boot initializes the devices on the board and checks if the board is System Controller (slot-1). If so, it enables the FGA-002 arbiter.

  • Page 191: Figure 6. Boot Up Procedure

    FGA Boot Software SYS68K/CPU-30 R4 Technical Reference Manual Figure 6: Boot up procedure Actions / State The Boot ROM (at address FFE0.0000 ) is mapped to 0000.0000 The CPU loads its initial stack pointer (SSP) and initial program counter (PC)

  • Page 192: Figure 7. Boot Up Procedure (Continued)

    SYS68K/CPU-30 R4 Technical Reference Manual FGA Boot Software Figure 7: Boot up procedure (continued) Actions / State Check for Firmware Module to start: is variable Start Module at Address even ? (see Note 1) is firmwarebase defined ? (see Note 2)

  • Page 193: As - Line Assembler

    FGA Boot Software SYS68K/CPU-30 R4 Technical Reference Manual 10.1 AS - Line Assembler Format: AS <address> The AS command invokes the line assembler of the FGA-002 Boot Software. It can assemble and disassemble all 68020/30/40 mnemonics and 68881/82 floating point instructions.

  • Page 194: Cont - Continue With Calling Routine

    SYS68K/CPU-30 R4 Technical Reference Manual FGA Boot Software The disassembler displays all illegal or unknown opcodes as DC.W. Example: FORCE-BOOT> AS 8000 $00008000 : ORI.B #0,D0 : MOVE.L #$123,D1 $00008006 : ORI.B #0,D0 : -6 move 6 bytes back $00008000 : MOVE.L #$123,D1 : <Ctrl-A>...

  • Page 195: Di - Disassembler

    FGA Boot Software SYS68K/CPU-30 R4 Technical Reference Manual 10.3 DI - Disassembler Format: DI <address> DI <address>,<count> The DI command causes the disassembler to be invoked and displays the mnemonic, starting at the specified address. If the count parameter is given, the specified number of lines (mnemonics) will be displayed.

  • Page 196: Ferase - Erase Flash Memories

    SYS68K/CPU-30 R4 Technical Reference Manual FGA Boot Software 10.5 FERASE - Erase Flash Memories Format: FERASE <flashbank> FERASE <flashbank>,<flashoffset>,<length> The FERASE command allows to erase Flash Memory banks. The first format of the command erases the whole Flash Memory bank.

  • Page 197: Fprog - Program Flash Memories

    FGA Boot Software SYS68K/CPU-30 R4 Technical Reference Manual 10.6 FPROG - Program Flash Memories Format: FPROG <flashbank>,<source> FPROG <flashbank>,<source>,<flashoffset> FPROG <flashbank>,<source>,<flashoffset>,<length> The FPROG command allows to program Flash Memory banks. The first format of the command programs the whole Flash Memory bank with the data stored at the specified source address.

  • Page 198: Go - Go To Subroutine

    SYS68K/CPU-30 R4 Technical Reference Manual FGA Boot Software Example: FORCE-BOOT> FPROG Usage: FPROG <flashbank>,<source>[,<flashoffset>[,<length>]] Parameter <flashbank> is the base address of the flash bank or one of the following defines: BOOT_FLASH1 BOOT_FLASH2 SYS_FLASH1 FORCE-BOOT> FPROG BOOT_FLASH1,100000 Do not reprogram BOOT_FLASH1, this would destroy the booter Device is write protected FORCE-BOOT>...

  • Page 199: Lo - Load S-Records To Memory

    FGA Boot Software SYS68K/CPU-30 R4 Technical Reference Manual 10.8 LO - Load S-Records to Memory Format: LO [<host commands>] LO <offset> [,<host commands>] LO V [,<host commands>] LO <offset>,V [,<host commands>] LO E The LO command allows to load S-Records from the console port into memory and to verify the memory contents.

  • Page 200: Netload - Load File Via Network To Memory

    SYS68K/CPU-30 R4 Technical Reference Manual FGA Boot Software FORCE-BOOT> LO 200 add offset 200 to addresses use ’~C’ to execute local command ~CLocal command? cat test.x use ’cat test.x’ to transfer file away for 2 seconds FORCE-BOOT> DI 100200 5...

  • Page 201: Netsave - Save Data Via Network To File

    The following commands save the memory region 10.0100 10.011F into the file ’test’. The content of the file will be overwritten. FORCE-BOOT> BF 100100 100120 "# Another Test #" P FORCE-BOOT> MD 100100 20 00100100: 23 20 41 6e 6f 74 68 65...

  • Page 202: Setup - Change Initialization Values

    SYS68K/CPU-30 R4 Technical Reference Manual FGA Boot Software 10.11 SETUP - Change Initialization Values Format: SETUP F or SETUP SETUP S The SETUP command is used to change SRAM parameters. ’SETUP F’ and ’SETUP’ allow to modify the initialization values of the FGA-002 as described in the FGA-002 User’s Manual.

  • Page 203: Slot - Change Slot Number And Vmebus Slave Address

    FGA Boot Software SYS68K/CPU-30 R4 Technical Reference Manual 10.12 SLOT - Change Slot Number and VMEbus Slave Address Format: SLOT <slot number> The SLOT command allows to modify the VMEbus slave address, the VMEbus address of the Mailbox Array (register MYVMEPAGE of the FGA-002) and the FMB slot number (register FMBCTL) as follows: VMEbus slave address (A32)= 8000.0000...
  • Page 204 SYS68K/CPU-30 R4 Technical Reference Manual FGA Boot Software Example: The following example sets the VMEbus slave address of the board to 8300.0000 and the window size to 1 Mbyte. It can now be accessed from 8300.0000 to 830F.FFFF FORCE-BOOT> VMEADDR 83000000,100000 Use the INIT command to recalculate the SRAM checksum ! FORCE-BOOT>...

  • Page 205: The Fga Boot Utility Interface

    FGA Boot Software SYS68K/CPU-30 R4 Technical Reference Manual The FGA Boot Utility Interface The FGA Boot Software provides several utility functions which can be called from within a user’s application. This section describes all additional functions not listed in the FGA-002 User’s Manual.
  • Page 206 SYS68K/CPU-30 R4 Technical Reference Manual FGA Boot Software From programming language C, the call could be made as follows (i.e., return version string): #define BootROM 0xFFE00000 main() long (*util)(long fctNo, ...); long ret; util = *((long **) (BootROM + 0x0008));...
  • Page 207 FGA Boot Software SYS68K/CPU-30 R4 Technical Reference Manual #37 (0x25) Erase Flash Memories The function allows partial erasing of Flash Memory banks if the devices support page erasing mode. Syntax: long util (37, flashbank, offset, length) Parameters: flashbank Base address of the Flash Memory bank that should be erased.
  • Page 208 SYS68K/CPU-30 R4 Technical Reference Manual FGA Boot Software #38 (0x26) Get System Values in SRAM This function sets a pointer to the base address of the System Values stored in the SRAM. It also returns the size of this structure (#of bytes).
  • Page 209 FGA Boot Software SYS68K/CPU-30 R4 Technical Reference Manual #40 (0x28) Get Ethernet Number This function copies the board’s Ethernet number (6 bytes) to the specified buffer. The return value contains the status of this operation. Syntax: long util (40, intfNumb, pEtherAdr) Parameters: intfNumb Interface number, must be set to 0.

Table of Contents