Circuit Description - Kenwood DPF-K6010V Service Manual

1. MPEG Microprocessor : IC11 (E3210F)
Pin description
No. Name
1 VDD
2 RAS
3 DWE
4~12 MA0~MA8
13~28 DBUS0~DBUS15
29 RESET
30 VSS
31 VDD
32~39 YUV0~YUV7
40 VSYNC
41 HSYNC
42 CPUCLK
43 PCLK2X
44 PCLK
45 (GFS) AUX0
46 (SQSO) AUX1
47 (VFD D) AUX2
48 (MUTE) AUX3
49 (IRQ) AUX4
50 VSS
51 VDD
52 VFD L
53 STB
54 VFD CK
55~62 LD0~LD7
63 LWR
64 LOE
65~67 LCS (3, 1, 0)
68~79 LA0~LA11
80 VSS
81 VPP
82~87 LA12~LA17
88 ACLK
89 AOUT/SEL PLL0
90 ATCLK
91 ATFS/SEL PLL1
92 DOE
93 AIN
94 ARCLK
95 ARFS
96 TD MCLK
97 TD MDR
98 TD MFS
99 CAS
100 VSS

CIRCUIT DESCRIPTION

I/O
– Voltage supply for 3.3V.
O DRAM row address strobe (active low).
O DRAM write enable (active low).
O DRAM multiplexed row and column address bus.
I/O DRAM data bus.
I System reset (active low).
– Ground.
– Voltage supply for 3.3V.
Y is luminance, UV are chrominance data bus for screen
O
Video interface. YUV (0~7) for 8 bit YUV mode.
I/O Vertical sync for screen video interface, programmable for rising or falling edge.
I/O Horizontal sync for screen video interface, programmable for rising or falling edge.
RISC and system clock input.
I
CPUCLK is used only if SEL PLL [1 : 0] = 00.
I/O Pixel clock ; two times the actual pixel clock for screen video interface.
I/O Pixel clock qualifier in for screen video interface.
I/O GFS input from IC2 (CXD2500BQ).
I/O Inputs 80 bit Sub Q and 16 bit PCM peak-level data.
I/O Auxiliary control pins.
I/O "H" for muting, "L" for release.
I/O Auxiliary control pins.
– Ground.
– Voltage supply for 3.3V.
I/O Auxiliary control pins.
I/O Auxiliary control pins.
I/O Auxiliary control pins.
I/O RISC interface data bus.
O RISC interface write enable (active low).
O RISC interface output enable (active low).
O RISC interface chip select (active low).
O RISC interface address bus.
– Ground.
– Digital supply voltage for 5V.
O RISC interface address bus.
Master clock for external audio DAC (8.192MHz, 11.2896MHz, 12.288MHz, 16.9344
I/O
MHz, and 18.432MHz).
O Dual-purpose pin. AOUT is the audio interface serial data output
Pins SEL PLL [1 : 0] select phase-lock loop (PLL) clock frequency CPUCLK for the
ES3210 : 00 = bypass PLL.
I 01 = 54MHz PLL.
10 = 67.5MHz PLL.
11 = 81MHz PLL.
I/O Audio transmit bit clock.
O Dual-purpose pin. ATFS is the audio interface transmit frame sync.
Pins SEL PLL [1 : 0] select phase-lock loop (PLL) clock frequency CPUCLK for the
I
ES3210. See the SEL PLL0 pin above for the settings.
O DRAM output enable (active low).
I Audio interface serial data input.
I Audio receive bit clock.
I Audio interface receive frame sync.
I TDM interface serial clock.
I TDM interface serial data receive.
I TDM interface frame sync.
O DRAM column address strobe bank 0 (active low).
– Ground.
DPF-K6010V
Description
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