Kenwood DV-5050M Service Manual page 21

Port No. Port Name
91 VSYNC/CREFO
92 H/CSYNCO
110 FILM
SDRAM Interface Signals
125~131 ADDR(4~10)
133~136 ADDR(0~3)
139~143,146~150 DATA(0~4)
153~157,160~166 5~9,10~14,
169~176 15~21,22~29
118 MEMCLKO
119 WEN
120 RASN
121 CASN
122 BSEL
• Simplified Block Diagram
Ext. Syncs /
PIXCLK
10
/
RGB/YUV/Y
/
CrCb/D1
/
2
DADDR
/
SDA
SCL
DV-5050M/5900M/DVF-J6050/J6050-G
CIRCUIT DESCRIPTION
I/O
Vertical sync output. This signal provides the vertical sync function
O
for the outputs.
Horizontal or composite sync output. This signal provides the horizontal sync
O
function for the outputs.
O Film mode detector output.
SDRAM address bus. This signal bus is used to address
-
the external SDARM(s) used for field memories.
SDRAM data bus. This signal bus is used to transfer the data to and from
-
the external SDRAM(s) used for field memories.
O SDRAM clock and 2x output sampling clock.
SDRAM write enable. This active low signal should be connected
-
to the WE pin(s) on the SDRAM(s).
SDRAM row address select. This active low signal should be connected to
-
the RAS pin(s) on the SDRAM(s).
SDRAM column address select. This active low signal should be connected to
-
the CAS pin(s) on the SDRAM(s).
- SDRAM bank select.
PLL/Clock
PLl/Clock
Generator
Generator
Deinterlacer Core with DCDi
Input
Motion Compensation, Film
Signal
Mode Detection and Bad Edit
Formatter
Control
Interface and
Registers
Function
TM
,
Correction
Sync
Sync Out
Generator
10
YU V
Output
/
/RGB/
/
Signal
/
YCrCb
Formatter
21