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DV-5050M/5900M/DVF-J6050/J6050-G
6-4 Digital Video Enhancer : FL12220 (X35, IC703) DV-5900M only
• Port Function
Port No.
External OSD Interface
1~5
156~160
6
144~153
Test outputs(Not shown on Block diagram)
7~10
13~15
Test inputs(Not shown on Block diagram)
19
69,70,143
Power Supply Connections(Not shown on Block diagram
11,28,40,49,59,60,81,
87,93,99,101,107,
113,119,121,127,
131,135,141,154
12,29,41,50,79,80,82,
88,94,100,102,108,
114,120,122,128,
132,136,142,155
72
68
74
Control Signals
16
17
18,20
21~23
24
25
67
139
Input Signals
26,27,30~37
43~48,51~54
55~58,61~66
Input Signals(cont.)
38
39
42
Analog Output Signals
71
73
75
76
77
78
18
CIRCUIT DESCRIPTION
Port Name
I/O
OSDC(0~4)
I
Multiplexed chroma signal is input on this bus. ( Connected to ground.)
OSDC(5~9)
OSDSEL
-
External OSD select input. (Connected to ground.)
OSDY(0~9)
-
External OSD luma input. (Connected to ground.)
TEST(03~06)
O
Test outputs. These pins should be left unconnected for normal operation.
TEST(00~02)
TESTB
I
Active low test input. This pin should be tied to VDD for normal operation.
TEST (0~2)
I
Active high test inputs. This pin should all be tied to VSS for normal operation.
Digital power connections. Connect to the digital +3.3 volt power
VDD
-
supply and decouple to the digital ground plane.
VSS
-
Digital ground connections. Connect to the digital ground plane.
Analog current sink return for the video DAC circuits. Connect to the analog
ISINK
-
ground plane.
AVDD
-
Analog power connections for the clock PLL circuits.
AVDD
-
Analog power connections for the video DAC circuits.
SDA
I
I
2
C compatible serial control bus data.
SCL
I/O I
2
C compatible serial control bus clock.
MODE(0,1)
-
I
C operating MODE( 0,1).
2
The setting of ADDR(0~2) allow the I
ADDR(0~2)
-
programmed to prevent conflict with the other I
I
2
CCLK
I
Clock input for the internal I2C circuit.
Reset. When this input is set low it will reset all internal registers
RESETB
I
to the default states.
CLKIN
I
Master clock input.
ENHOFF
-
When this pin is set low the FL12220 will be in normal enhancement mode.
CBIN(0~9)
I
10-bit non-multiplexed Cb or multiplexed Cb/ Cr signal input bus.
CRIN(0~9
I
10-bit non-multiplexed Cr signal input bus.
YIN(0~9)
I
10bit luminance or multiplexed Y/Cb/Cr signal input bus.
HBLANKI
I
Horizontal input blanking signal.
VBLANKI
I
Vertical input blanking signal.
FLDIN
I
Odd/Even field designator input.
R/Cr-ANA
O
Analog output.
G/Y-ANA
O
Analog output.
B/Cb-ANA
O
Analog output.
Compensation for video DACs. Should be connected to analog
COMP
-
groundvia a capacitor.
RSET
-
Current setting resistor for video DACs.
VREF
-
Voltage reference for video DACs.
Function
C address of the device to be
2
2
C devices in the system.
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