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DV-5050M/5900M/DVF-J6050/J6050-G
6-5 Video Deinterlacer : FL12200(X35, IC700) DV-5900M only
• Port Function
Port No.
Test outputs
112,113
TEST(00, 01)
Test inputs
41,50,51,108
109,111
Power Supply Connections(Not shown on Block diagram)
1,33,63,73,84,95
105,114,123,137
144,151, 167
2,17,34,55,64,74
85 ,96,106,115
124,132, 138,145
152,159,168
43
16,54,107,158
42
Control Signals
49
53
56~58
IFORMAT(2~0)
59~61
OFORMAT(2~0)
44,45
46
47
48
40
62
Control Signals(contd.)
52
Input Signals
18~27
6~15
28~32
35~39
3
HSYNCREFI
4
VSYNCREFI
5
Output Signals
65~72
G/YOUT(2~9)
75,76
93,94
B/CbOUT8,9
97~104
B/CbOUT(0~7)
77~83
R/CrOUT(3~9)
86~88
R/CrOUT(0~2)
116
117
89
90
20
CIRCUIT DESCRIPTION
Port Name
I/O
O
These pins are test outputs and should be left unconnected in normal operation.
These pins are used for test purposes only and should always be tied low
TEST(0~5)
-
for normal operation.
Pad Ring digital power connections. Connect to the digital +3.3 volt power
VDD33
-
supply and decouple to the digital ground plane.
VSS
-
Ground connections. Connect to the digital ground plane.
AVSS
-
Ground connection for the clock PLL circuits. Connect to the digital ground plane.
Core Logic digital power connections. Connect to the digital +2.5 volt
AVDD25
-
power supply and decouple to the digital ground plane.
Analog power connections for the clock PLL circuit. Connect to a separately
AVDD
-
decoupled +2.5 volt power supply and decouple directly to the AVSS pin.
Reset. When this input is set low it will reset all the internal registers
RESETB
I
to the default states.
When this pin is set high the the outputs of the FL12200 will be enabled ; when
OE
O
it is set low the outputs will be set into a high-impedance state.
I
Input signal format control.
O
Output signal format control.
The settings of DADDR(1,0) allow the device address of the control bus to
DADDR(1,0)
-
be programmed to prevent conflict with the other devices connected to the bus.
When this pin is set low the control bus will operate in the slave mode; allowing
MODE
-
the device to programmed from an external controller.
SDA
I
2-wire serial control bus data.
SCL
I/O
2-wire serial control bus clock.
PIXCLK
I
Pixel clock input. This clock is used to drive all the circuits in the FL12200.
N/P/IN/OUT
I/O
NTSC/PAL input or output.
NOMEM
I
No memory mode control input.
G/YIN(0~9)
I
10-bit green or luminance signal input bus.
B/CbIN(0~9)
I
10-bit blue or Cb chroma signal input bus.
R/CrIN(0~4)
I
10-bit red or Cr chroma signal input bus.
R/CrIN(5~9)
I
Horizontal sync or reference.
I
Vertical sync or reference.
FIELDIN
I
Field identifier input.
O
Green or luminance output bus.
G/YOUT0,1
O
Blue or Cb chrominance output bus.
O
Red or Cr chrominance output bus.
CCLKO
O
Chroma output sampling clock.
YCLKO
O
Luma output sampling clock.
VREFO
-
Start of active field or frame indicator.
HREFO
O
Start of active line indicator output.
Function
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