Philips A02E Service Manual page 69

Circuit Descriptions, Abbreviation List, and IC Data Sheets
registers are added to compensate this. The video signal is
only analysed when it is within a programmable
(measurement) window. This window coincides with a
rectangular shaped part of the (visible) picture. Normally
this is the centre part of the picture.
Memory Based Features (MBF)
The Memory Based Features (MBF) block embodies a set of
functions that require (shared) memory.
The main and sub video streams can be spatially compressed
in order to produce a mixed output in the form of several PIP
combinations or DW.
The main video stream can be passed through a temporal
noise reduction circuit (DNR).
The 3D Comb filter is also implemented in this block.
The main and sub streams are merged when reading from
memory. The merged video stream can be up-converted to
either a double line rate (progressive scan) or to a double field
rate (100 Hz). The up-conversion is done by means of a digital
scan function. Following figure shows the functional block
diagram of the video memory based features (MBF).
7300
ADOC MBF
SUB
HOR. VERT. NOISE
CH. COMPRESS COMPRESS SHAPER
(YUV)
SUB
FIFO
CACHE
MAIN
MAIN
HOR. NOISE
FIFO DNR
CH.
COMPRESS SHAPER
CACHE
(YUV)
MODE CONTROL
Figure 9-12 MBF block diagram
Back End Features (BEF)
The Back End Features (BEF) block embodies a collection of
spatial picture enhancement functions.
The video display has to be blanked during AV switching,
channel switching, V-chip, and Child Lock modes. This is done
inside the BEF block of the ADOC IC. The fast blanking signal
input from SCART1and SCART3 (TV SCART inputs) for RGB
video insertion is connected to the ADOC IC.
Sharpness functions are:
•
Luminance Transient Improvement (LTI),
•
Dynamic Peaking, and
•
Digital Colour Transient Improvement (DCTI).
The panorama block does the non-linear scaling for displaying
4:3 formats on a wide-screen display.
Colour enhancement functions are:
•
Skin Tone Control,
•
Blue Stretch, and
•
Green Enhancement.
A colour Space Converter can convert the video signal from
YUV to RGB format. The Frame Processing block can insert
frames and borders such as a coloured frame around the
Picture in Picture (PIP). Following figure shows the structure of
the Back End Feature block.
7730
SDRAM
1,14,27
VDDE VDD
3,9,43,49
VDDQ
FIELD MEMORY & TXT PG
SA0...SA11
7300-I SD0...SD15
MEMORY
DTL I/F
CTRL/SWI.
MEMORY
UNDI-
BUS
THER SCAN
DEVICE
RATE
INTERF.
CONVERT
UNDI-
THER
OUTPUT Y
UNDI-
MUX.
THER
UV
DISPLAY CONTROL
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A02E
7300
13.5 / 27 MHz 27 / 54 MHz
@ 720 ppl @ 1440 ppl
LUMINANCE SHARPNESS
SHARPNESS
F
I
MEASURE
L
LTI
T
E
DYN.
Y
Y R
PEAKING
PANO-
RAMA
U Y
SKIN
U
UV DCTI TONE
STRETCH
V V
CONTROL
COLOUR FEATURES
Figure 9-13 BEF block diagram
Digital Output Processor (DOP)
The DOP is a display processor block, and contains the
following functions:
•
RGB control processor with linear RGB input for the main
video signal, a linear RGB input for OSD/text signals with
blending, and an RGB output stage with black current
stabilisation which is realised with the continuous cathode
calibration (2-point black current measurement) system.
•
Programmable deflection processor, driven by an
external crystal clock, which generates the drive signals for
the horizontal, east-west, north-south and vertical
deflection with extensive geometry correction capabilities.
•
The circuit can be used in both single scan (50 or 60 Hz)
and double scan (100 or 120 Hz) applications.
X-PROT
ADOC DOP
1st 1st 2nd SLOW START/STOP SLOW START/STOP
HVSYNC
CONTROL CONTROL CONTROL
B5 LOOP LOOP LOOP L0W POWER STARTUP L0W POWER STARTUP
SEL2FH HOR. TIMEBASE GEN. Hor. TIMEBASE GEN.
DTO & CONTROL LOOP DTO & CONTROL LOOP
VERT. VERT.
DRIVER SAWTOOTH
BPA
DOP-DTC-VDDA
DOP-DTC-VDD3
IMEAS-VDDA
SDAC-3V3
SDAC-VDDA
Figure 9-14 DOP block diagram
RGB Control Processing
•
The RGB control circuit of the DOP contains two sets of
input signals:
–
The first RGB input (RGB), 10 bits wide, is intended for
the normal video signals coming from the BEF part.
The "RGB" signals will first enter a contrast control
stage, followed by a brightness control stage, both
influenced by a combination of user control, Beam
Current Limiter and Peak White Limiter, followed by a
soft clipper stage. Then the signal will be applied to the
blender stage. The blender input signal will be used as
an input for the peak white limiting system.
–
The second RGB input (GFX), 4 bits wide, is intended
for OSD and Teletext signals. The switching between
the internal signal and the OSD signal is realised via a
blending function. The "GFX" input signals will be re-
formatted to 10 bit wide internally before entering the
Beam Current Control brightness correction stage,
followed by the hard clip stage. Then the signal will also
be applied to the blender stage.
•
The two input data streams are combined into one stream
by the blender. This blender is controlled by a third data
stream.
•
The next block is the "Drive Adjust" part. It contains a
Picture Tube Biasing system, a Beam Current Control, and
Peak White Limiting part.
9. EN 101
ADOC BEF
R
RGB FRAME TO
G
MATRIX PROC. B7
Y
BLUE GREEN B
U
ENHANCE
V
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HIRES. HIRES.
HDROUT LINE DRIVERS
TIMING TIMING
GEN. GEN.
EHT EHT INFO
ADC
EAST-WEST
BCL
WAVEFORM
POR FLASH
FBCIN
FRAME DRIVE+
VDRP
VERT.
SDAC SDAC
VDRN FRAME DRIVE -
WAVEFORM
EWP EW-DRIVE
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