Philips A02E Service Manual page 67

Circuit Descriptions, Abbreviation List, and IC Data Sheets
Primary
colour
decoder
Second Main Front
ary Sub End
I2D
colour select Features
Link
decoder
128KB
SRAM
Memory
SOUND SOUND SOUND
Dem.
Dec. Switch
(DSP)
DAC
I2S L/R/HP/MON/...
Figure 9-9 ADOC block diagram
The dual stream architecture of the ADOC system allows audio
and video processing of two A/V sources simultaneously. The
two video streams can be displayed in several programmable
ways (main screen, PIP or DW). The two audio streams are
audible via the TV loudspeakers and/or the headphones.
For the memory-based features (like scan rate conversion, 3D-
Comb filtering, dynamic noise reduction, and PIP/DW
applications), external SDRAM is used (item 7730).
The ADOC also has 128 kBytes of internal SRAM memory.
This memory is used to run low latency, timing critical parts of
the software. The internal memory is also used if the system
operates in a single scan 50/60 Hz interlace application without
any other kind of memory based features. Under these
circumstances, no external SDRAM is needed.
Some ADOC features:
•
Video Decoding:
–
2-Colour Decoder (PAL, NTSC, SECAM).
–
2D and 3D Comb filter.
•
Memory Based Features:
–
PIP/DW, DNR, Scan Rate conversion.
•
Picture Improvements:
–
CTI, LTI, Colour correction.
•
Digital Output Processor:
–
RGB processing, Scavem, Deflection control.
•
Audio Processing:
–
Demodulator/Decoder (A2, NICAM, BTSC).
–
Tone, Volume, Balance, Dolby ProLogic.
•
VBI (Vertical Blank Interval) Services:
–
Teletext, Closed Caption, V-chip.
•
TV Control:
–
I2C, UART, IR, Keyboard.
•
Graphics:
–
Character based.
Video Decoding (VIDDEC)
The Video Decoder (VIDDEC) is the video input processor and
colour decoder. There are two VIDDECs: the primary and the
secondary VIDDEC. The VIDDEC processes all CVBS, Y/C,
and 1fH/2fH component (e.g. RGB) video input signals.
Control Video Sound
SDRAM
SDRAM
MMI
Back RGB
Memory Digital
based End Output
Defl.
Features Features Processor
MIPS
Graphics
PR1910
AUDIO
Features EBIU
Peripherals
Interface
(DSP)
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ROM/FLASH/SRAM
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A02E
DMSD=Digital Multi Standard Decoder
7300-J
STROBE1N
ADOC VIDDEC (PRI & SEC)
EXT. STEREO
STROBE1P
I2D1
DATA1N
Sync
PRI
Mux.
DATA1P
STROBE3N
CHR.
STROBE3P
I2D3
DATA3N
DATA3P
STROBE2N
SS IF
STROBE2P
SEC
I2D2
DATA2N
DATA2P
EXT. MONO
H-2FH
Ext
SRC for
V-2FH Syn
HFB1/
c
FBL-SC1-IN H-Sync
Mux
HV_PRIM
HV_SEC
Figure 9-10 VIDDEC block diagram
Primary VIDDEC (1fH/2fH)
The primary VIDDEC supports the following functionality:
•
Conversion of the digitised samples from MPIF into
orthogonal samples (meaning fixed number of pixels per
line, independently of line frequency).
•
Correction for any amplitude errors of the input signals
(CVBS, YC, or YCbCr) by means of an Automatic Gain
Control (AGC).
•
Standard detection of PAL/NTSC or SECAM and various
1fH/2fH component input formats.
•
Colour decoding for PAL, NTSC, or SECAM input signals.
•
Sync identification (to be used for channel search).
•
Sync processing for any 1fH or 2fH input signal.
•
Fast-blank insertion of RGB signals (supplied via MPIF) on
CVBS input signals.
•
2D Comb filtering. 3D Comb filtering is implemented in the
Memory Based Feature block of the Feature Box.
Secondary VIDDEC (1fH)
The secondary VIDDEC is mainly intended for use with PIP/
DW. It supports the following functionality:
•
Conversion of the digitised samples from MPIF into
orthogonal samples (meaning fixed number of pixels per
line, independently of line frequency).
•
Correction for any amplitude errors of the input signals
(CVBS) by means of an Automatic Gain Control (AGC).
•
Standard detection of PAL/NTSC or SECAM and various
1fH component input formats.
•
Colour decoding for PAL, NTSC, or SECAM input signals.
•
Sync identification (to be used for channel search).
•
Sync processing for any 1fH input signal.
•
CVBS 1fH input signals only.
Data Synchroniser and Sample Rate Converter
The data synchroniser is a de-multiplexer that separates the
UV stream into a separate U and V data stream. The sample
rate converter converts the video samples from the crystal
clock domain to the so-called line locked clock domain, 720
pixels per line.
Automatic Gain Control (AGC)
The AGC amplifier block controls the gain of the signal and is
controlled directly by the chassis software. This gain will
depend on the amplitude of the output signal (signal amplitude
and/or sync amplitude) as measured by the AGC gain block. As
a secondary function, it controls both the offset at the input and
the offset at the output of the gain control.
Digital Multi Standard Decoder (DMSD)
This DMSD block contains the following functionality:
9. EN 99
VDDCO VDDE
DMSD
DE-
MUX
MUX
B8
HVSYNC
VIDDEC2
FAST- FAST
FOR-
BLANK BLANK B6
MATER
FIFO SWITCH
VIDDEC1
SYNC
HV
2Fh
INFO
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