Yamaha CRD-HD1300 Service Manual page 37

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IC3 : YDC126-F (MAIN P.C.B.)
ACDR
No. Name
97 RD1
98 RD0
99 VDD
100 RA12
101 RA11
102 RA10
103 RA9
104 RA8
105 RA7
106 VSS
107 RA6
108 RA5
109 RA4
110 RA3
111 RA2
112 RA1
113 RA0
114 VSS
115 /ROE
116 /RWE
117 /RAS
118 /CAS
119 MUTSP
120 MUTAE
121 AVSS
122 PCO
123 AVDD
124 /LOCK
125 /TESTA
TE
126 /TESTB
L 13942296513
127 VSS
128 XI
129 XO
130 F256A
131 VDD
132 DINA
133 DINB
134 DINC
135 DOUT
136 DDIN
137 SI
138 SO
139 /CSO
140 SCK
141 DIRINT
142 UBIT
143 VSS
144 SYNCA
145 WCA
146 F128A
147 F64A
148 EXTW
149 EXWI
150 WCB
151 F256B
152 F64B
153 SYNCC
154 WCC
www
155 F128C
156 F64C
157 VSS
158 DWCKI
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159 DWCKO
160 VDD
I/O I: Input O: Output I/O: Bi-directional $: Clock signal OT: Tri-state output
+: Pull-up resistor built-in A: Analog terminal OD: Open drain
DC C: CMOS level T: TTL level
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I/O DC Level Function
I/O T/C External RAM interface, data bus
I/O T/C External RAM interface, data bus
Power supply +5V
O C External RAM interface, address output
O C External RAM interface, address output
O C External RAM interface, address output
O C External RAM interface, address output
O C External RAM interface, address output
O C External RAM interface, address output
GND
O C External RAM interface, address output
O C External RAM interface, address output
O C External RAM interface, address output
O C External RAM interface, address output
O C External RAM interface, address output
O C External RAM interface, address output
O C External RAM interface, address output
GND
O C External RAM interface, read strobe output
O C External RAM interface, write strobe output
O C External RAM interface, lower address strobe output
O C External RAM interface column address strobe output
I T SPD pin mute control input, muting provided at "1"
I+ T Unconnected
Analog GND for PLL
A Capacitance connection terminal for PLL
Analog power supply for PLL +5V
O C Master clock, PLL lock detect output
I+ T Unconnected (testing terminal)
I+ T Unconnected (testing terminal)
GND
I$ C 24.576MHz crystal oscillator connection terminal (input)
O$ C 24.576MHz crystal oscillator connection terminal (output)
O$ C Master clock, dividing clock output (256fs)
Power supply +5V
I+ T Digital audio interface input A
I+ T Digital audio interface input B
I+ T Digital audio interface input C
O C Digital audio interface output
I T Serial audio data input
I+ T DIR5 interface, control data input
O C DIR5 interface, control data output
O C DIR5 interface, chip select output
O$ C DIR5 interface, bit clock output
I+ T DIR5 interface, interrupt input
I+ T DIR5 interface, U-bit signal input
GND
O C Master clock system, synchronous signal output
O$ C Master clock system, word clock output (fs)
O$ C Master clock system, dividing clock output (128fs)
O$ C Master clock system, dividing clock output (64fs)
O$ C Word clock output (fs)
I$+ T External word clock input (fs)
I$ T Digital input data system, word clock input (fs)
I$ T Digital input data system, dividing clock input (256fs)
I$ T Digital input data system, dividing clock input (64fs)
I+ T Unconnected
I$+ T Mode switching, "1": normal operation, "0": PLL constant output mode
I$+ T Unconnected
I$+ T Unconnected
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y GND
I$ T Drive word clock input (44.1kHz or 33.8688MHz)
i
O$ C Drive word clock output (for charge couple)
Power supply +5V
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