Page of 56
TGL
check
points
I.
Voltage check
of
power supply
Check that
a
voltage
of +5V
(±5Si!)
is
input at the
VDD
pin.
4.75V
^
VDD
^
5.25V
2.
Check of input/output
pins,
regardless
of the CPU interface
setting
PiN NAME
FUNCTION
BCKO
2.0 MHz bit clock signal
outputs
to the
D/A converter.
LRCKO
31.25 KHz L/R clock signal output
to the D/A
converter.
If
the
voltage
level
of these pins
is
+ZS
or less,
check the soldering
of
peripheral pins and
the
voitage
of the
connected device.
Also,
if
any of these pins
is
OV or
+5V,
check
to
see whether RESET(TGRES)
or
the master cIock(32.0MHz) has been
input.
If
RESET and HCK are normal
and the test node setting pins have been set as below,
check the soldering and
the
pattern
on the
circuit
board.
3.
Check of input/output pins, when the
key on
PIN NAME
FUNCTION
XCS,
XfE
Control signal from the CPU
During KEY
ON or PROG. CHANGE,
check that
a low level
pulse signal
is
input froB the CPU to the
above pins(XSC,
XWE).
If
these signals cannot
be
observed with the oscilloscope, check
the CPU and its
peripheral
circuits.
PIN NAME
FUNCTION
SDOO, SDOl
serial data output to the D/A converter
In
case of observing the
wavefon
with the oscilloscope,
it
is
best
to
input the
LRCKO clock signal
to the
external trigger input
of
the oscilloscope.
If
the serial data cannot be output, check the PCM
address
bus.
To find whether
nonal
serial data
is
output
or not,
check whether there
is
a
different
bit from the code bit at the left side
of the leading and the
trailing edge of LRCKO
on the
oscilloscope
screen.
LRCKO
SDO
I
I
I
I
I
i
[
I
I
I
I
m
**
sign
M
S
B
swing
level
L
$
B
34

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