D-Board Block Diagram - Panasonic TH-42PD50U Service Manual

Digital progressive wide plasma television
Hide thumbs Also See for TH-42PD50U:
Table of Contents

Advertisement

13.39. D-Board Block Diagram

D
DIGITAL SIGNAL PROCESSOR
FORMAT CONVERTER,
PlASMA AI
SUB-FIELD PROCESSOR
TO DG5
D5
E+LVDS0
1
E-LVDS0
2
E+LVDS1
4
E-LVDS1
5
E+LVDS2
6
E-LVDS2
7
E+LVDS3
9
E-LVDS3
10
E+LVDS4
11
E-LVDS4
12
E+LVDSCLK
14
E-LVDSCLK
15
LVDS_DET
16
0+LVDSCLK
17
0-LVDSCLK
18
STB 5V
TO DG3
D3
STB 5V
12
DRVMUTE
DISPEN
6
READY
READY
7
ALARM
ALARM
8
IIC_CLK1
19
P3V_SCL1
IIC_DATA1
20
P3V_SDA1
Q9000
PANEL_STB_ON
11
FAN_CONT
FAN_CONT(FAN_MAX)
1
FAN_SOS
FAN_SOS
3
ECO_ON
ECO_ON
4
F_STBY_ON
TUNER_SUB_ON
14
FOR
FACTORY
D4
Q9004
Q9001
USE
TXD_PC
10
TXD
RXD_PC
RXD
11
IIC_INT
IIC/INT
12
SDA2
SDA2
7
SCL2
SCL2
6
SDA1
SDA1
5
SCL1
SCL1
4
IIC_CONT
IIC_CONT
2
P12V
TO P25
D25
+12V
1
P5V
+12V
2
STB5V_M
+5V
7
+5V
9
STBY5V
10
FAN_CONT
FAN_CONT
3
FAN_SOS
FAN_SOS
14
F_STBY_ON
F_STBY_ON
13
ECO_ON
ECO_ON
15
PANEL_MAIN_ON
PANEL_MAIN_ON
17
PS_SOS
PS_SOS
16
FOR
FACTORY
D6
USE
DCLK
1
CONF_DONE
DCLK
CONF_DONE
3
NCONFIG
nCONFIG
5
NCE
DATA0
nCE
6
2
DATA
DCLK
DATA0
7
nCS
8
1
NCS
ADSI
ASDIO
9
NCS
PSTB
11
ASDI0
PBUSY
13
PDB0
15
PSLCT
17
PDB1
19
DCDC_ON
16
XRST
18
3.3V
4
3.3V
3.3V
14
TH-42PD50U
D-Board Block Diagram
IC9300
FORMAT CONVERTER/RGB PROCESSOR
R 10bit
G 10bit
I/P
FORMAT
CONVERTER
CONVERTER
B 10bit
VD
HD
DCK
PCK
DPCLK5 DPCLK2
LVDS
R0
G0
B0
VD
HD DCK
DISCHARGE
Low
R9
G9
B9
CONTROL
Voltage
Differential
PICTURE OUTPUT
Signaling
RECEIVER
IC9500
FPGA/SYNC/OSD/DISCHARGE CONTROL
FPGA CONTROL
NCS
NCS
DATA0
DATA0
CONF_DONE
CONF_DONE
NCONFIG
NCONFIG
ASDI0
ASDI0
NCE
NCE
R,G,B,HD,VD,CK
DCLK
CONTROL
DCLK
SCL
SDA
P3V_SCL2
P3V_SDA2
IC9008
STB5V_M
AVR STB3.3V
STB3.3V
SW
Q9003
2
AVR
4
1
ON/OFF
IC9001
EEPROM
SDA
5
SCL
6
P3V_SCL2
Q9008
P3V_SDA2
Q9009
3.3V
P12V
D2
D1
Q9702
G2
S2
G1
S1
IC9007
6
Ex.I/O
26
23
27
24
5
SW1
BG2
TG2
VIN
RUN/SS1
1
PLASMA AI/SUB FIELD PROCESSOR
CTI/TINT
COLOR
R 10bit
SUB-FIELD
CONTRAST
G 10bit
NEW PLASMA AI
WB-ADJ
PROCESSOR
B 10bit
st-r
XRST
OCK
11
CLK8
X9200
X1
1
IC9200
14 CLK5
CLKM_IN
7
CLK1
CLOCK GENE.
X2
20
FREE_RUN
IC9303
10
CLK4
32M FLASH MEMORY
RESET
IC9503
LEVEL CONVERTER
3.3V
5V
DATA POWER
FEEDBACK
IC9504
LEVEL CONVERTER
Control DATA
3.3V
DATA DRIVER
IC9502
SS PULSE
LEVEL CONVERTER
Sustain Control DATA 6bit
3.3V
5V
SCAN OUT
SC PULSE
UMH,UML,USH,USL,UEH,NUEL
OSD
DRV_RST
3.3V
5V
Scan Control DATA 13bit
NRST
DRVMUTE
CL,CLK,SIU,SID,SCSU,CEL2,CPH,CEL,CBK,CSL,CSH,CML,CMH
IC9005,06
LEVEL CONVERTER
49
XRST
50
NRST
14
DRV_SOS2
OSD
DRV_SOS9
19
DRV_SOS7
TXD_PC
DRVRST_DATA
21
TXD1
IC9003
RXD_PC
22
RXD1
MICOM
IIC_CONT
65
IIC_CONT
IIC_INT
78
IIC_INT
Q9012
P3V_SCL1
SCL1
85
STB_SCL1
P3V_SDA1
Q9013
SDA1
84
STB_SDA1
SCL2
67
STB_SCL2
SDA2
66
STB_SDA2
ALARM
71
ALARM
READY
72
READY
P5V_DET
3.3V_DET
P12V_DET
PANEL_MAIN_ON
48
PANEL_MAIN_ON
1.5V
PS_SOS
98
PS_SOS
D2
D1
Q9701
G2
S2
G1
S1
REM_IN
41
P_ON/OFF
17
19
16
SW2
BG2
TG2
IC9702
RUN/SS2
DC_DC CONV.
15
Q9703
Q9704
95
IC9302
DDR SDRAM(64M)
D34
Video DATA
24bit(DA,DB,DC8-15)
DATA
DRIVER
Video DATA
24bit(DA,DB,DC0-7)
DRVCLKD0-D3
CLKD3
CLKD2
SCL
P3V_SCL2
SDA
P3V_SDA2
(PCD2)
Q9900
P5V
IC9301
RESET
3.3V
4
VOUT
VCC
5
DSHL,DSLL,DMHL,DMLL,DMHR
ODED,CLRD,LED,PCD1,PCD2
5V
CLKD1
CLKD0
(PCD1)
Q9700
Q9901
P5V
SOS2
SOS2
SOS9
SOS2
99
R9028
SOS9
97
SOS7
92
Q9011
57
D20
XIN
28
X9000
9.216MHz
XOUT
26
P5V
5V(P)
STB3.3V
SOS7
SOS2
IC9004
RESET
30
RESET
RESET
P5V
Q9023
Q9022
3.3V
93
P12V
94
95
Q9021
Q9020
LED_G
LED_G
70
LED_R
LED_R
69
REMOCON
10
Q9010
LED_G
LED_R
STB5V_M
IC9700
REM
AVR 2.5V
VCC
CTL
OUT
2
1
4
3.3V
2.5V
TH-42PD50U
D-Board Block Diagram
TH-42PD50U
TO C11
9
DATA L
14
23
L-DOWN
42
20
DATA L TIMING
21
16
DATA DRIVE
19
45
5V_DET
52
P5V
55
47
DATA
POWER
FEED BACK
51
DRVRST
44
D33
TO C21
8
DATA R
R-DOWN
34
40
DATA R TIMING
41
36
DATA DRIVE
39
51
SUSTAIN
DATA
46
5
5V_DET
4
P5V
1
43
DRV_SOS2
44
DRV_SOS9
6
DRVRST
TO SC20
2
9
SCAN
13
DATA
20
1
P5V
11
DRV_SOS7
12
DRV_SOS2
NOT USED
D8
LED_G
2
3
LED_R
6
REMOCON
1
STB5V

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents