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_MIDI_RST
13MHz
I2S_SCK
I2S_WS
I2S_SDO
1V8_MV
2V8_MV
R312
0
C324
C327
C325
0.1u
0.1u
1u
CPU INTERFACE
CPU interface is an 8-bit parallel.
4 control signal(/wr,/rd,/cs,A0 pin), 8 data bit(D0 to D7), and 1 interrupt pin(/IRQ), totaling 13 pins are
connected to the external CPU. This block controls the writing and reading of data by the input polarity
of control signal
INTERFACE REGISTER
This registeris able to access directly ffrom the external CPU. There are 2 bytes spaces. The
Intermediate register can be accessed through the interface register.
INTERMEDIATE REGISTER
This register is accessed through the Interface register.
It is composed to access a latter control register and ROM/SRAM through Intermediate register.
This register is called "Intermediate register" since this exists in the middle of the interface register and
the Control register.
In the Intermediate register, there are some registers to control various functions.
TP300
B4
_RST
1000p
G5
CLKI
C307
D2
BLCK
D3
LRCK
D1
SDI
D6
GPIO0
YMU787
C5
GPIO1
C1
GPIO2
C4
GPIO3
B1
LED2_GPIO5
C2
LDE1_GPIO4
C3
LED0
B2
MTR
VBAT
C328
C329
C330
C326
1u
1u
0.1u
10u
Figure 3-24. YMU787 CIRCUIT DIAGRAM
- 43 -
3. TECHNICAL BRIEF
100p
C300
82K
82K
R301
R300
C301
1000p
27K
R305
R307
0.01u
3.3K
C304
B8
SPOUT2L
B7
SPOUT1L
H8
SPOUT2R
J8
SPOUT1R
U300
E8
TXOUT
D7
EXTOUT
G7
EXC
E6
BBL
C8
HPOUTL
E7
BBR
C7
HPOUTR
C322
C323
0.1u
1u
SPK_N
C310
470p
C311
C312
R311
47p
47p
3.3
SPK_P
MIDI_HP_L
MIDI_HP_R
C315
C316
C317
0.1u
0.1u
1u
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