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3. TECHNICAL BRIEF
This speeds up frequency settling and ensures that the PLL control voltage never operates close to the
rails. DFC is the result of an adaptive circuit that corrects for any VCO center frequency errors caused by
variations of the integrated VCO circuit such as temperature, supply voltage, or aging. The VCO can be
centered at any frequency in the range from 990 MHz to 1550 MHz. Once centered, the VCO has a
minimum analog tuning range of 20 MHz. No calibration or data storage is needed for DFC operation. It is
activated by one of two events:
• When the synthesizer is programmed, the rising edge of the LE signal starts the DFC cycle
• When the SXENA signal level is changed from low to high, which enables the synthesizer, the rising edge
of the SXENA signal starts the DFC cycle.
C. Integrated Loop Filters
Both loop filters (for the UHF PLL and for the transmit PLL) are fully integrated. Several adjustments can be
made to the loop filter transfer functions. The UHF loop filter has two synchronized charge pumps. The
frequency of the "zero" factor (z1) in the PLL phase transfer function can be adjusted by varying the charge
pump currents, and the values of the internal R3 resistor and C3 capacitor.
Charge Pump Current Compensation for Constant PLL Bandwidth The VCOs in the SKY74400 use
Skyworks DFC technique. The nature of the DFC circuit increases the VCO control sensitivity
(KVCO) as
the VCO frequency is increased. Without any compensation, this leads to an increase in the PLL loop gain
and an increased loop bandwidth for higher frequencies. In a classical PLL design, KVCO is typically
regarded as a constant. In this case, the loop gain decreases with increased frequency as the division ratio
of the loop is increased proportionally to frequency. Since it is usually desirable to keep the loop bandwidth
constant over the frequency range of interest, the SKY74400 includes a circuit that compensates the charge
pump current to keep the overall loop gain constant.
Charge pump current compensation for the UHF PLL can be programmed to one of three settings (nominal,
high, or low) or the charge pump current can be programmed to a constant value without compensation.
Refer to the Skyworks Programming Guide SKY74117 RF Transceiver for Standalone Devices or
Embedded MCMs for details.
D. Crystal Oscillator
A 26 MHz crystal oscillator provides the reference frequency for the synthesizer. the oscillator uses an
external 26 MHz crystal to generate an accurate oscillation frequency. The reference frequency can be
changed through coarse-tuning with an integrated capacitor array or fine-tuning with the integrated varactor
diode. The oscillator is coarse-tuned by switching in and out (using a digital word programmed with the
serial interface) the capacitor network (CAP_A and CAP_B) located at the input of the integrated buffer. The
oscillator is fine-tuned by providing a tuning voltage to the integrated varactor diode.
An output buffer is provided to drive the baseband circuitry. The frequency of the output is determined by
the FREQ_SEL signal. When this signal is connected to ground, the output is 13 MHz; when connected to
VCC or left floating, the output is 26 MHz. The oscillator core powers up when the SXENA signal is set to
logic 1.
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