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HCD-AZ2D/AZ5D
QQ
3 7 63 1515 0
Pin No.
Pin Name
IOA2 to IOA8,
53 to 61
IOA18, IOA19
62
DVSS
63
APLLCAP
64
APLLVSS
65
VDD3
66
IOWR
67 to 72
IOA16 to IOA11
73
DVDD3
74 to 76
IOA10, IOA9,IOA20
77
IOCS
78
IOA1
79
IOOE
80
DVDD3
81 to 84
AD0 to AD3
85
DVSS
86 to 88
AD4 to AD6
89
IOA21
90
ALE
91
AD7
92, 93
IOA17, IOA0
94
DVSS
TE
95
UWR
L 13942296513
96
URD
97
DVDD18
98
IFSDO
99
IFCK
100
XIFCS
101
IFSDI
102
SCL
103
SDA
104
TRG-SW
105
IFBSY
106
RXD
107
TXD
108
DVDD3
109
ICE
110
PRST
111
IR
112
INT0
113
DQM0
114
MREQ
www
115
RD7
116
DVSS
117, 118
RD6, RD5
.
119
DVSS
120, 121
RD4, RD3
122
DVDD18
68
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I/O
O
Address signal output to the flash ROM
–
Ground terminal
–
Connection terminal for an external capacitor
–
Ground terminal
–
Power supply terminal (+3.3V)
O
Write enable signal output to the flash ROM
O
Address signal output to the flash ROM
–
Power supply terminal (+3.3V)
O
Address signal output to the flash ROM
O
Chip select signal output to the flash ROM
O
Address signal output to the flash ROM
O
Output enable signal output to the flash ROM
–
Power supply terminal (+3.3V)
I/O
Data/address signal input/output terminal with the flash ROM
–
Ground terminal
I/O
Data/address signal input/output terminal with the flash ROM
O
Address signal output to the flash ROM
O
Address latch enable signal output terminal Not used
I/O
Data/address signal input/output terminal with the flash ROM
O
Address signal output to the flash ROM
–
Ground terminal
O
Write enable signal output terminal Not used
O
Data read enable signal output terminal Not used
–
Power supply terminal (+1.8V)
O
Serial data output to the system controller
I
Serial data transfer clock signal input from the system controller
I
Chip select signal input from the system controller
I
Serial data input from the system controller
O
Serial data transfer clock signal output to the EEPROM and D/A converter
I/O
Two-way data bus with the EEPROM and D/A converter
I
Trigger detection switch input terminal
I
Busy signal input from the system controller
Receive data input terminal for UART communication when data writing to
I
flash memory
Transmit data output terminal for UART communication when data writing to
O
flash memory
–
Power supply terminal (+3.3V)
I
ICE mode enable signal input terminal Not used
I
Reset signal input from the system controller "L": reset
I
IR control signal input terminal Not used
O
Interrupt request signal output terminal Not used
O
Data mask signal output to the SD-RAM
O
Muting request signal output to the system controller
I/O
Two-way data bus with the SD-RAM
x
ao
u163
–
Ground terminal
y
I/O
Two-way data bus with the SD-RAM
i
–
Ground terminal
I/O
Two-way data bus with the SD-RAM
–
Power supply terminal (+1.8V)
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2 9
8
Description
Q Q
3
6 7
1 3
1 5
co
.
9 4
2 8
0 5
8
2 9
9 4
2 8
m
9 9
9 9
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