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KD-S687
TC9490FA (IC521) : DSP
1. Pin layout & Block diagram
2. Pin function (1/2)
No.
Symbol
I/O
1
BCK
2
LRCK
3
AOUT
4
DOUT
5
IPF
6
VDD3
7
VSS3
8
SBOK
9
CLCK
I/O
10
DATA
11
SFSY
12
SBSY
13
/HSO
14
/UHSO
15
PVDD3
16
PDO
17
TMAX
18
LPFN
19
LPFO
20
PVREF
21
VCOF
22
AVSS3
23
SLCO
24
RFI
25
AVSS3
1-24
48
47
46
45
44
DV
49
SS3
Clock
RO
50
generator
DV
51
DD3
LPF
DVR
52
1-bit
DAC
LO
53
DV
54
DD3
55
ZDET
V
56
SS5
57
BUS0
BUS1
58
59
BUS2
BUS3
60
Audio output
61
BUCK
circuit
Micro-
62
/CCE
controller
interface
63
/RST
V
64
DD5
1
2
3
4
5
O
Bit clock output pin.32fs, 48fs, or 64fs selectable by command.
O
L/R channel clock output pin. "L" for L channel and "H" for R channel.
O
Audio data output pin. MSB-first or LSB-first selected by command.
O
Digital data output pin. Outputs up to double-speed playback.
O
Correction flog output pin.
-
Digital 3.3V power supply voltage pin.
-
Digital GND pin.
O
Subcode Q data CRCC result output pin. "H" level when result is OK.
Sub-code P-W data read clock I/O pin. I/O polarity selectable by command.
O
Sub-code P-W data output pin.
O
Playback frames sync signal output pin.
O
Sub-code block sync output pin.
O
Playback speed mode flag output pin.
O
Playback speed mode flag output pin.
-
PLL-only 3.3V power supply voltage pin.
O
EFM and PLCK phase difference signal output pin.
O
TMAX detection result output pin.
I
Inverted input pin for PLL RF amp.
O
Output pin for PLL LPF amp.
-
PLL-only VREF pin.
O
VCO filter pin.
-
Analog GND pin.
O
DAC output pin for data slice level generation.
I
RF signal input pin.
-
Analog 3.3V power supply voltage pin.
43
42
41
40
39
38
37
PWM
Servo control
Digital equalizer
ROM
Address
automatic
circuit
RAM
adjustment circuit
CLV servo
16 k
RAM
Sync signal
protection
EFM
Digital output
Sub code
decoder
6
7
8
9
10
11
12
Function
36
35
34
33
32 TEZI
31
TEI
D/A
30
SBAD
29
FEI
A/D
28
RFRP
27
RFZI
26
RFCT
AV
25
DD3
24
RFI
Data
slicer
23
SLCO
22
AV
SS3
VCO
21
VCOF
20
PV
REF
19
LPFO
PLL
TMAX
18
LPFN
TMAX
17
13
14
15
16
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