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KD-S687
PT6523LQ(IC601) :
1.Terminal layout
48
49
64
1
2.Block diagram
3.Piin function
Pin No.
Pin Name
1~ 52
SG1 ~ SG52
53~55
COM1 ~ COM3
56
57
58
59
60
61
62
63
64
Note 1. When INH = "LOW" : Serial data trensfers can be performed when the display is forcibly OFF.
1-22
~
33
32
17
~
16
COMMON
DRIVER
CLOCK
GENERATOR
ADDRESS
DETECTOR
I/O
O
O
VDD
-
INH
I
VDD1
I
VDD2
I
VSS
-
OSC
I/O
CE
I
CLK
I
DI
I
SEGMENT DRIVER & LATCH
SHIFT REGISTER
Description
Segment Output Pins
Common Driver Output Pins
Power Supply
Display OFF Control Input Pin
When this pin is "Low", the Display is forcibly
turned OFF. (SG1 to SG52, COM1 to COM3 are
set to "LOW"). (See Note 1)
When this pin is set to "High", the Displa is ON.
Used for the 2/3 Bias Voltage when the Bias Voltages
are provied externally. Connect to VDD2 when
1/2 Bias is used.
Used for 1/3 Bias Voltage when the Bias Voltages
are provided externally. Connect to VDD1 when
1/2 Bias is used.
Ground Pin.
Oscillation Input /Outout Pin
Chip Enable Pin
Synchronization Clock
Transfer Data Pin
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