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3 7 63 1515 0
• IC701 CL680T-D1 (AUDIO/VIDEO MPEG DECODER)
Pin No.
1
2
3
4
5
6
7 – 9
10 – 15
16
17
18
19
20
21
22
23 – 28
29
30 – 36
37
38
39
40
41
TE
L 13942296513
42
43
44, 45
46
47
48
49
50 – 52
53
54
55
56 – 58
59
60
61
VDDMAX_IN
62 – 64
65
AGND_DAC
66
AVDD_DAC
67
COMPOS_OUT
68
AGND_DAC
69
70
AVDD_DAC
71
AGND_DAC
www
72
73
74
AVDD_DAC
.
75
76
AGND_DAC
77
CLK_SEL [0]
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Pin Name
I/O
NC
—
Not used. (Open)
VSS
—
Ground
CD_BCK
I
CD decode bit clock signal (2.8224 MHz) input from the CXD3037R (IC601).
CD_DATA
I
CD decode data input from the CXD3037R (IC601).
CD_LRCK
I
CD decode L/R sampling clock signal (44.1 kHz) input from the CXD3037R (IC601).
CD_C2PO
I
CD decode C2 error data input from the CXD3037R (IC601).
NC
—
Not used. (Open)
MD0 – 5
I/O
Two-way data bus with the program ROM (IC704) and DRAM (IC703).
VSS
—
Ground
MD6
I/O
Two-way data bus with the program ROM (IC704) and DRAM (IC703).
VDD3
—
Power supply pin (+3.3 V)
MD7
I/O
Two-way data bus with the program ROM (IC704) and DRAM (IC703).
VSS
—
Ground
MD8
I/O
Two-way data bus with the program ROM (IC704) and DRAM (IC703).
VDD3
—
Power supply pin (+3.3 V)
MD9 – 14
I/O
Two-way data bus with the program ROM (IC704) and DRAM (IC703).
MD15
I/O
Two-way data bus with the program ROM (IC704).
NC
—
Not used. (Open)
MCE
O
Chip enable signal output to the program ROM (IC704).
MWE
O
Write enable signal output to the DRAM (IC703).
VSS
—
Ground
CAS
O
Column address strobe signal output to the DRAM (IC703).
VDD3
—
Power supply pin (+3.3 V)
RAS0
O
Row address strobe signal output to the DRAM (IC703).
RAS1
O
Row address strobe signal output (Not used in this set)
MA10, 9
O
Address signal output to the program ROM (IC704).
MA8
O
Address signal output to the program ROM (IC704) and DRAM (IC703).
VSS
—
Ground
MA7
O
Address signal output to the program ROM (IC704) and DRAM (IC703).
VDD3
—
Power supply pin (+3.3 V)
MA6 – 4
O
Address signal output to the program ROM (IC704) and DRAM (IC703).
VSS
—
Ground
MA3
O
Address signal output to the program ROM (IC704) and DRAM (IC703).
VDD3
—
Power supply pin (+3.3 V)
MA2 – 0
O
Address signal output to the program ROM (IC704) and DRAM (IC703).
PGIO7
I/O
Connect to VSS in this set.
RESET
I
Reset signal input from TMP87CM41U (IC803). ("L": Reset)
I
Fix the maximum input voltage each input pin and input/output pin.
NC
—
Not used. (Open)
—
Ground (for D/A converter)
—
Power supply pin (+3.3 V) (for D/A converter)
O
Composite video signal output
—
Ground (for D/A converter)
Y-OUT
O
Luminance video signal output (Not used in this set)
—
Power supply pin (+3.3 V) (for D/A converter)
—
Ground (for D/A converter)
RREF
I
Fix the video signal output level control.
x
ao
VREF
O
Reference voltage (+1.235 V) output
y
—
Power supply pin (+3.3 V) (for D/A converter)
i
C-OUT
O
Chrominance video signal output (Not used in this set)
—
Ground (for D/A converter)
I
Clock select 0 input (Fixed at "H" in this set)
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8
Q Q
3
6 7
1 3
u163
.
– 13 –
2 9
9 4
2 8
Pin Description
1 5
0 5
8
2 9
9 4
m
co
9 9
2 8
9 9
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