Clock - Philips DVDR890 Service Manual

EN 210 9. DVDR880-890 /0X1
LINK_AVVALID
LINK IC Audio/Video data valid
LINK_CSN
LINK IC chip select
LINK_INTN
LINK IC interrupt
LINKFIFO_DQ(0:7)
Audio Video data interface
PA(0:15)
SRAM processor address
PAD(0:7)
SRAM processor data
PALE
Processor Address Latch Enable
PHY_CNA
PHY 1394 cable not active
PHY_LPS
LINK IC power status
PINT0N
Processor interrupt 0
PINT1N
Processor interrupt 1
PRDN
Processor read
PROGRAMN
Low active input to initiate a configuration cycle
PRSTN
Processor reset
PWRN
Processor write
RASN
Row address strobe
RESETN
DVIO board reset
RTSN
System Reset
RXD
Receive Data
SRAMCE0N
SRAM processor chip enable 0
SRAMRDN
SRAM processor output enable
TCK
Boundary scan Test Clock
TDI
Boundary scan Test Data Input
TDO
Boundary scan Test Data Output
TDO_CONF
Boundary scan Test Data Output from IC 7309
TMS
Boundary scan Test Mode Select
TXD
Transmitted Data
UCASN
Upper column address strobe
WEN
Write Enable control signal to SRAM
YUV(0:7)
Digital Video
Analog Board
+5VSTBY
Permanent Supply 5V
8SC2
Pin8 Scart2 (only for Europe)
A_DATA
Data from Analog- to Digital-Board (UART-Communication)
A_RDY
Analog-board ready (status information to digital-board)
A18 - A19
Parallel Address Bus (CC - Flash-ROM and S-RAM)
A8 - A17
Parallel Address Bus (CC - Flash-ROM and S-RAM)
Circuit-, IC Descriptions and List of Abbreviations
AD0 - AD7
Parallel Address and Data Bus (CC - Flash-ROM and S-RAM)
AFC
Automatic Frequency Control
AFEL
Audio Frontend Left
AFER
Audio Frontend Right
AGC / WSRI
Automatic Gain Control (for Europe), Wide Screen Rear In (for
NTSC)
AINFL
Audio In Front Left
AINFR
Audio In Front Right
AKILL
Audio Kill Signal
ALADC
Audio Left to ADC
ALDAC
Audio Left from DAC
ALE
Address Latch Enable
AM0
Adress-mode 0
AM1
Adress-mode 1
ARADC
Audio Right to ADC
ARDAC
Audio Right from DAC
ASCC1M
Audio Scart 1 Mute (System Clock Output for Real time Clock-
Adjustment)
AVCC
Power Supply for A/D-converter
AVSS
GND-Pin for A/D-converter
CFIN
Chroma Front In
CS0_
Chip Select 0 (CC - S-RAM)
CS2_
Chip Select 2 (CC - Flash-ROM)
CVBSFIN
Video Front In
D_DATA
Data from Digital- to Analog-Board (UART-Communication)
D_RDY
Digital-board ready (status information from digital-board)
DAC_MUTE
Mute Signal for DAC
DAOUT
Digital Audio Out
DVAL
Audio from Digital Video In Left
DVAR
Audio from Digital Video In Right
DVCC1
Power Supply Pin
DVCC2
Power Supply Pin
DVCC3
Power Supply Pin
DVSS1
GND Pin
DVSS2
GND Pin
DVSS3
GND Pin
FAN_OFF
Fan for Basic engine
FBIN
Fast Blanking input
FOME