Clock - Philips DVDR890 Service Manual

Circuit-, IC Descriptions and List of Abbreviations
Composite video/Luminance input to Video Input Processor
CVBS_Y_IN_C
Composite video/Luminance input to Video Input Processor
D_ADDR(10:0)
Address bus
D_DATA(29:0)
Data bus
D_EMPRESS(15:0)
SDRAM data input/output of EMPRESS
D_PAR_D(7:0)
Front-end parallel interface data (record)
D_PAR_DVALID
Front-end parallel interface data valid
D_PAR_REQ
Front-end parallel interface request
D_PAR_STR
Front-end parallel interface strobe
D_PAR_SYNC
Front-end parallel interface sync
DV_IN_CLK
Digital Video in clock from DVIO board
DV_IN_DATA(7:0)
Digital Video in data bus from DVIO board
DV_IN_HS
Digital Video in horizontal synchronisation from DVIO board
DV_IN_VS
Digital Video in vertical synchronisation from DVIO board
EMI_A(21:1)
External Memory Interface Address Bus(Host Decoder)
EMI_BE0N
External Memory Interface Lower byte enable(Host Decoder)
EMI_BE1N
External Memory Interface Upper byte enable(Host Decoder)
EMI_CAS0N
External Memory Interface SDRAM column address
strobe(Host Decoder)
EMI_CE1N
External Memory Interface VSM Lower bank enable
EMI_CE2N
External Memory Interface VSM Higher bank enable
EMI_CE3N
External Memory Interface flash IC's enable
EMI_D(15:0)
External Memory Interface Data Bus(Host Decoder)
EMI_PROCCLK
External Memory Interface Processor Clock(Host Decoder)
EMI_RWN
External Memory Interface Read/Write control signal(Host
Decoder)
EMI_WAIT
External Memory Interface Wait state request(Host Decoder)
EMPRESS_BOOT
EMPRESS BOOT select input
EMPRESS_IRQN
EMPRESS Interrupt request output
FLASH_OEN
FLASH output enable control signal
G_IN_VIP
Video green input to Video Input Processor
G_OUT
Video green output from Host Decoder
G_OUT_B
Filtered green video output from Host Decoder
GNDD
Digital Ground
HD_M_AD(13:0)
Host Decoder SDRAM address bus
HD_M_CASN
Host Decoder SDRAM column address strobe
HD_M_CLK
Host Decoder SDRAM clock
HD_M_CS0N
Host Decoder SDRAM chip select
HD_M_DQ(15:0)
Host Decoder SDRAM data bus
DVDR880-890 /0X1
HD_M_DQML
Host Decoder SDRAM data mask enable(Lower)
HD_M_DQMU
Host Decoder SDRAM data mask enable(Upper)
HD_M_RASN
Host Decoder SDRAM row address strobe
HD_M_WEN
Host Decoder SDRAM write enable
HSOUT
Horizontal synchronisation OUT
ION
Inverted ON: Enable the power supply for the digital board
when LOW
IRESET_DIG
Initialisation of the digital board, HIGH when power ON
JTAG3_TCK
JTAG Test Clock
JTAG3_TD_VIP_TO_VE
JTAG Transmitted Data Video Input Processor to Video
Encoder
JTAG3_TD_VSM_TO_VIP
JTAG Transmitted Data Versatile Stream Manager to Video
Input Processor
JTAG3_TMS
JTAG Test Mode Select
JTAG3_TRSTN
JTAG Test part ResetN
LOAD_DVN
LOAD Digital Video(LOW active)
MUTEN
Mute enable
MUTEN_LV
Mute enable Low Voltage
P_SCAN_YUV(7:0)
Progressive Scan digital video bus
R_IN_VIP
Video Red input to Video Input Processor
R_OUT
Video Red output from Host Decoder
R_OUT_B
Filtered Red Video output from Host Decoder
RAS
Row Address Strobe
RESETN
Reset Host Decoder
RESETN_BE
System reset basic engine (buffered)
RESETN_DVIO
System reset Digital Video Input Output (buffered)
RESETN_VE
System reset Video Encoder
ROMH_CEN
Flash 2 chip enable
ROML_CEN
Flash 1 chip enable
RSTN_BE
Reset control of basic engine
RSTN_DVIO
Reset control of DVIO
RTS1P
Ready To Send data to service serial interface
RX1P
Receive data from service serial interface
SCL
I2C bus clock
SD_CASN
SDRAM Column Address strobe output (active LOW)
SD_CLK
SDRAM clock output
SD_CLKE
SDRAM clock enable output
SD_CSN
SDRAM
SD_DQM(1:0)
SDRAM data mask enable output
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