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7. CIRCUIT DIAGRAM
1
1
2
2
3
3
Battery Charging Circuit
A
A
VCHG_VBUS
Route together from both end of resistor 0.1ohm.
1%
ISNS_P
U401
NUS5530MN
ISNS_M
10
Drain_B
2012
1
9
NC1
Collector_B
2
8
Collector
Emitter
3
7
+VPWR
Source
Base
4
6
VBAT
Drain
NC2
5
Gate
C402
C401
33u
0.01u
B
B
C
C
D
D
Move PCB Rev ADC to PMIC side at Rev.C
R409
10
VCHG_VBUS
PCB_Rev_ADC
rev.A=>none
rev.B=>150K : 10K : 0.16V
rev.C=>150K : 47K : 0.62V
rev.D=>150K : 68K : 0.81V
rev.E=>150K : 100K : 1.04V
VREG_MSMP_2.6V
rev.F=>150K : 150K : 1.30V
rev.1.0=>150K : 300K : 1.73V
rev.1.1=>150K : 470K : 1.97V
E
E
R411
R412
470K
1%
150K
1%
M7
MPP_1
N5
PROX_ADC
MPP_2
D8
REMOTE_PWR_ON
MPP_3
B12
MPP_4
D4
MSM_USIM_RST
MPP_5
A1
SIM_RST
MPP_6
L12
MPP_7
M11
GSM_PA_DAC_REF
MPP_8
K8
MSM_USIM_CLK
MPP_9
K9
SIM_CLK
MPP_10
K5
MSM_USIM_DATA
MPP_11
K6
SIM_IO
MPP_12
M3
MPP_13
N1
F
F
MPP_14
N3
MPP_15
M5
MPP_16
B3
MPP_17
D5
MPP_18
F4
USBH_CS
MPP_19
G4
NOTE : 1.8V MPP19 for USB HS
MPP_20
J2
MPP_21
K2
MPP_22
Route together
H2
USB_ID
L2
USB_DP
USB_D_P
M2
USB_DM
USB_D_M
H4
USB_OE_N
J4
USB_DAT
K4
USB_SE0
J10
VREG_MSMP_2.6V
SBST
H10
SBCK
K10
PMIC_SSBI
SBDT_SSBI
D10
G
G
PM_INT_N
MSM_INT_N
B6
SPKR_IN_L_M
B7
SPKR_IN_L_P
A6
SPKR_OUT_L_M
A7
SPKR_OUT_L_P
B4
SPKR_IN_R_P
B5
SPKR_IN_R_M
A4
SPKR_OUT_R_P
A5
SPKR_OUT_R_M
B2
VIDEO_IN
B1
VIDEO_OUT
N2
VIB_DRV_N
E1
KPD_DRV_N
KPD_DRV_N
F1
LCD_DRV_N
H1
FLSH_DRV_N
H
H
OJ401
OJ402
OJ403
OJ404
1
1
2
2
3
3
LGE Internal Use Only
4
4
5
5
6
6
u-USB Connector
TA OVP Circuit
VREG_MSMP_2.6V
CN401
6
8
10
2mm
12
1
2mm
2
3
9
DRAIN_THERMAL
4
ID
5
8
VCC
7
9
7
OUT
GND
11
13
6
CHG_CTL_N
GATE
CNTRL
5
BATT_FET_N
SRC
DRAIN
For OVP test
C405
U402
NUS3065MUTAG
3900p
50V
+VPWR
Close to u-USB connector
U404
NLAS7222C
1
10
D+
S
Exchange DP and DM for layout.
2
9
D-
VCC
3
8
GND
_OE
rev 1.0
4
7
USB_DP_TX
HSD2-
HSD1+
rev 1.0
5
6
USB_DM_RX
HSD2+
HSD1-
USBH_SEL
S/W
LOW
1 (USBH)
HIGH
2
VBAT
+VPWR
Route together
Place close to PM7540 pins
C414
0.1u
C415
0.1u
C416
0.1u
C418
C417
0.1u
33p
C419
0.1u
C420
0.1u
C421
0.1u
C422
0.1u
C424
C423
0.1u
1u
C425
0.1u
C426
0.1u
C427
0.1u
C428
1000p
C429
4.7u
+VPWR
C430
1000p
Place in PM7540 room at shield edge
C431
4.7u
C432
L401
2.2u
2.2uH
D402
C441
2.2u
K1
VSW_5V
J1
VREG_5V
L402
4.7uH
N8
RB521S-30
VSW_MSMC1
M8
VREG_MSMC1
VSNS_MSMC1_1.2V
L403
4.7uH
N6
VSW_MSMC2
M6
VREG_MSMC2
VSNS_MSMC2_1.2V
L404
4.7uH
N10
VSW_MSME
M9
L405
4.7uH
VREG_MSME
VSNS_MSME_1.8V
N4
VSW_PA
M4
VREG_PA
VSNS_SMPS
A2
VREG_GP1
J13
VREG_GP2
N12
VREG_GP3
A9
VREG_GP4
B13
VREF_GP5
E13
VREG_GP6
K13
VREG_MMC
A11
VREG_MSMA
C444
2.2u
G13
VREG_MSME2
U406
H13
VREG_MSMP
A8
VREG_RFRX1
PM7540
A10
VREG_RFRX2
A3
VREG_RFTX
N11
VREG_RUIM1
E12
VREG_SYNT
D13
VREG_TCXO
C448
2.2u
M1
VREG_USB
G1
VREG_WLAN
G12
MIC_BIAS
1%
A12
R419
121K
REF_ISET
A13
REG_GND
C13
C462
0.1u
REF_BYP
H12
TCXO_IN
TCXO_PM_19.2MHz
D9
TP408
TCXO_EN
TCXO_EN
G10
R420
51
TCXO_OUT
PMIC_TCXO
Place crystal and load caps close to PM7540
M13
XTAL_IN
N13
XTAL_OUT
CM315_12_5PF
K7
SLEEP_CLK
SLEEP_CLK
M12
AMUX_OUT
AMUX_OUT
Route together
C12
KPD_PWR_N
KPD_PWR_N
F10
PON_RESET_N
nPON_RST
D407
E10
PS_HOLD
KDS114E
R421
PRSB6.8C
D408
4
4
5
5
6
6
7
7
8
8
VCHG_VBUS
2mm
NFM18PC104R1C3
1
IN
OUT
GND1
GND2
1
IN
FL401
2
3
4
+VPWR
USBH_DM
USBH_DP
C406
U405
0.1u
SLAS4717EPMTR2G
rev 1.0
1
10
1K
USBH_SEL
VCC
NO2
UART3_RX
VCHG_VBUS
rev 1.0
2
9
rev 1.0
UART3_TX
NO1
COM2
USB_DM_RX
USBH_REF_CLK
rev 1.0
3
8
USBH_EN_N
USB_DP_TX
COM1
IN2
4
7
USBH_DM
USB_UART_SW
IN1
NC2
USB_DM
5
6
USBH_DP
USB_DP
NC1
GND
C413
0.1u
USB_UART_SW
S/W
LOW
NC (USB)
HIGH
NO (UART)
Local Ground Plan
These CAPs close to inductors
0.5mm
VREG_MSMC1_1.2V
0.5mm
VREG_MSMC2_1.2V
0.5mm
VREG_MSME_1.8V
0.3mm
VRF_SMPS
VREG_VGA_2.8V
VREG_LCD_2.8V
VREG_MOTOR_3.0V
VREG_HP_AMP_2.6V
VREG_AUX2_2.85V
PM_CAM_AF_2.8V
VREG_MMC_3.0V
VREG_MSMA_2.6V
VREG_MSMP_2.6V
VREG_RFRX_1
+2.7V
VREG_RUIM_3.0V
+2.75V
VREG_SYNTH
VREG_TCXO_2.85V
C463
22p
X401
32.768KHz
C464
22p
PS_HOLD
JTAG_PS_HOLD
200K
7
7
8
8
- 170 -
9
9
10
10
11
11
LGE Internal Use Only
USB Transceiver for High Speed
VREG_MSME_1.8V
+VPWR
C403
0.1u
C404
4.7u
10V
C4
C3
TEST
CHIP_SEL
USBH_CS
19.2MHz : CFG1 = L, CFG2 = L
B5
A4
TP401
26.0MHz : CFG1 = L, CFG2 = H
VCC_IO1
CLOCK
USBH_CLK
B2
B1
TP402
24.0MHz : CFG1 = H, CFG2 = L
VCC_IO2
DATA0
USBH_DATA[0]
13.0MHz : CFG1 = H, CFG2 = H
C2
A1
TP403
RREF
DATA1
USBH_DATA[1]
C1
A2
DM
DATA2
USBH_DATA[2]
D1
A3
U403
DP
DATA3
USBH_DATA[3]
E2
A5
ISP1508AET
FAULT
DATA4
USBH_DATA[4]
D3
A6
ID
DATA5
USBH_DATA[5]
B3
B6
CFG2
DATA6
USBH_DATA[6]
B4
C6
CFG1
DATA7
USBH_DATA[7]
D4
D5
TP404
PSW_N
NXT
USBH_NEXT
R406
F4
D6
TP405
VBUS
STP
USBH_STOP
E3
E5
TP406
REG3V3
DIR
USBH_DIR
F5
E1
XTAL1
CFG0
F6
E6
XTAL2
REF1V8
EUSY0320201
3.5pi Ear Jack Connector
VREG_MSMP_2.6V
FB602
VREG_MSMP_2.6V
U602
R1114D181D
C690 2.2u
1
3
VDD
VOUT
4
2
NC
GND1
6
5
HS_MIC_BIAS_EN
CE
GND2
TTY_ADC
7620-3_5G-DB1-A
J401
FB402
HS_MIC
EAR_SENSE
R416
30
HSL
R417
30
HSR
FM_ANT
FM_ANT
EAR_SENSE
LOW
Close
HIGH (detect)
Open
AGND
CONNECT TO U503.E3
9
9
10
10
11
11
Copyright © 2009 LG Electronics. Inc. All right reserved.
Only for training and service purposes
12
12
A
A
B
B
C
C
D
D
E
E
F
F
S/W
G
G
H
H
12
12
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