Sony CDP-M205 Service Manual page 9

Pin No. Pin name
37 VCTL
38 PCO
39 FILO
40 FILI
41 AVSS
42 CLTV
43 AVDD
44 RF
45 BIAS
46 ASYI
47 ASYO
48 ASYE
49 WDCK
50 LRCK
51 LRCKI
52 PCMD
53 PCMDI
54 BCK
55 BCKI
56 VSS
57 VDD
58 GTOP
59 XUGF
60 XPLCK
61 GFS
62 RFCK
63 C2PO
64 XRAOF
65 MNT3
66 MNT1
67 MNT0
68 XTSL
69 FSTT
70 C4M
71 DOUT
72 EMPH
73 EMPHI
74 WFCK
75 SCOR
76 SBSO
77 EXCK
78 VSS
79 VDD
80 SYSM
81 —
82 AVSS
83 AVDD
84 AOUT1
85 AIN1
86 LOUT1
87 AVSS
88 XVDD
89 XTAI
90 XTAO
I/O
I VCO2 control voltage input
O Charge-pump output to master PLL
O Filter output to master PLL
I Filter input for master PLL
– Analog ground
I Control voltage input for VCO
– Analog power supply
I EFM signal input
I Asymmetry circuit constant current input
I Asymmetry comparate voltage input
O EFM full swing output ("L" =VSS, "H" =VDD)
I Asymmetry circuit ON/OFF ("L"=OFF, "H"=ON)
O D/A interface Word clock f=2fs (Not used)
O D/A interface LR clock output f=Fs
I D/A interface LR clock input f=Fs
O D/A interface Serial data output
I D/A interface Serial data input
O D/A interface Bit clock output
I D/A interface Bit clock input
– Ground
– +5V power supply
– Not used
– Not used
O EFM decoder PLL clock output
O "H" Playback EFM sync and interpolation protection timming much
O Read Frame Clock signal output
– Not used
O Internal RAM overflow detection signal output (Not used)
– Not used
– Not used
– Not used
– Not used
O 2/3 divider output (Not used)
O 4.2336MHz output(Not used)
O Digital audio signal output
O Playback disc output in emphasis mode
I "H" =Input when de-emphasis ON
O Write Frame Clock signal output
O Sub-code sync output
O Sub-P through Sub-W serial output
I Clock input for SBSO read-out
– Ground
– +5V power supply
I System mute input (Connected to ground)
– Not used
– Analog ground
– Analog power supply
O Lch analog output
I Lch opamp input
O Lch line output
– Analog ground
– Master clock power supply
I X'tal oscillator circuit input
O X'tal oscillator circuit output
– 9 –
Description.