PS Audio DirectStream Junior Owner's Reference Manual page 6

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causing problems; we also control their transition times, thus limiting the amount of induced noise and
jitter into the main digital processing area.
6. Outputs of the FPGA use the slowest, lowest drive compatible with their function, keeping noise as
low as possible.
7. We use slower, older technology CMOS when we need CMOS. This choice lowers both noise and
jitter potential.
8. We use balanced signals when practical; they not only lessen radiation and are less sensitive to
Balanced
radiation, but they lessen noise in the ground and power rails.
Architecture
9. We use non-saturation logic so the exact transitions are more predictable. Coming out of saturation
is a statistical process.
10. High rate signals (or signals with fast edges) are isolated from control signals and especially each
Signal Isolation
other. If they have to be fast they are terminated appropriately to help address jitter.
Hand Selected
11. Jitter is addressed everywhere in the design. Every component choice, every signal connection,
every wire routed on the boards are all hand done to lower noise and pay attention to jitter.
Parts
12. 0.1% precision thin fi lm low temperature coeffi cient resistors are incorporated everywhere in the
audio path; 2% fi lm caps in critical places and 5% fi lm caps elsewhere in the audio path. By using
1/8W resistors or 1/4W resistors where others might use a 1/10W resistor, the temperature coeffi cient
of the resistors is lowered. For digital bypassing, NP0/C0G, or at worst, X7R MLCCs are used.
13. Low noise techniques are employed such as liberal use of low inductance capacitor bypassing
with a self resonance frequency at the main clock rate to keep noise from ever getting into the voltage
rails in the fi rst place.
14. Digital fi ltering in general, and the upsampling and noise shaping fi lters in the sigma-delta modulators
in particular, offer many degrees of freedom for a fi lter designer. There isn't a mathematically perfect
fi lter to use (they all have tradeoffs), so we've chosen the fi lters that sound best in our experience, and
in addition to that, we run everything with as wide of an audio bandwidth as possible.
15. Although design choices might have been made to run everything at single rate DSD (64 *
Double DSD
44100Hz), it was decided instead to run at double rate DSD to have a wider audio band below the
upsampling and noise shaping fi lters. Noise shaping is how a high rate sampled signal can have more
accuracy in part of the spectrum than the 6dB / bit rule and it is understood that the quantizer in a
sigma-delta modulator can hide a multitude of sins in the noise shaping fi lter. Our instrument still runs
the noise shaping fi lter at full precision to get the cleanest DSD signal possible.
16. No shortcuts are ever taken in the Digital Signal Processing (DSP) section of the FPGA. Despite the
fact that DSD is only nominally 20bit S/N, the design uses a minimum width of 24 bits throughout the
device. Where needed, very expensive (in terms of math operations) fi lters with wide coeffi cients and
144dB S/N are employed along with many guard bits in the IIR fi lters and the sigma-delta modulator.
17. Every trace on the PC board is hand routed: even for the digital sections. No autorouting is
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Introduction
Owner's Reference
Introduction
15-073-01-1
Rev A
DirectStream Junior
v