PS Audio DirectStream Junior Owner's Reference Manual page 5

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If the analog processing isn't linear and doesn't have a very wide bandwidth it will modulate the high
No Active Filtering
frequency noise that's inherent in DSD back into the audio band. That modulation will not result in just
low level noise. In practice it will be aliased back into the audible band with serious sonic consequences.
To maintain low noise and linearity, the design incorporates both high speed symmetrical video amps
and a passive output fi lter.
The fi rst challenge in such a design is the output switch that generates the fi nal 1's and 0's of the
Design Challenges
modulator. A very clean switch that hooks up the positive rail with a 1 and the negative rail with a 0 is
essential. If it has too much resistance, if the resistance is different at the positive end than the negative
end, if the resistance changes from time to time, ... the result will not be as clean as it needs to be.
For 120dB S/N, the switch resistance has to be quite consistent.
Another design requirement is consistent and fast switching time. If the switch is too slow it won't keep
up with the 5.6MHz signal used in this instrument. If the switch doesn't react in consistent times it will
introduce jitter. Use of traditional CMOS gates adds a lot of jitter as do cross-coupled totem-poled
bipolar transistors. Instead, DirectStream Junior relies on high speed differential video amps, which
are essentially class A switches, have their outputs either near the top rail or near the bottom power
supply rail (without ever saturating) and provide a very clean DSD switch.
For the all important low pass fi ltering requirements, an active fi lter adds self noise even if it is effectively
lowering incoming noise. A unique and effective solution to this problem is a passive fi lter.
The theory of operation, the fi rmware and the complex algorithms needed to execute a design of
this magnitude are daunting in their scale and scope. The actual hardware to run the instrument is,
perhaps, easier to grasp, although no less critical to the perfected performance.
Hardware Listed in this section are the highlights of the hardware, system's overview and design choices made
to create an instrument of this caliber.
Highlights
1. DirectStream Junior runs from one master clock designed to subtend all possible combinations of
sub-clocks, from 44.1, 88.2, 48, 96, etc in order to eliminate the need for multiple clocks that cause
errors and problems associated when noise from the unused clock propagates to the desired clock.
2. All sample rates supported are synchronously upsampled to 10x the standard DSD sample rate and
then back down to double rate DSD (2 * 64 * 44.1kHz). There's no need for other clocks to interpret
the inputs, no matter what their sample rate, because of the instrument's single clock architecture.
3. The path from the single master clock to its retiming fl ip-fl op path is designed as short as possible
and isolated from all other clocking.
Connection 4. Connections between sections of the design have large impedances, not only lots of power supply
isolation, but also, for example, 2k resistors in series with digital signals to slow down the edges and
Impedances
lessen any noise transfer.
5. Similarly, we run I2C, SPI and other control signals as slowly as they can possibly go without
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Introduction
Owner's Reference
Introduction
15-073-01-1
Rev A
DirectStream Junior
iv