Sony DVP-FX720 Service Manual page 53

Hide thumbs Also See for DVP-FX720:
Table of Contents

Advertisement

QQ
3 7 63 1515 0
Pin
number
193
YUV0/CIN
194
195
196
DACVDDC
197
ASDATA0/GPO_2
198
RVREF/GPIO_6
199
RCLKB/GPIO_5
200
201
202
ASDATA1/GPO_1
203
ASDATA2/GPO_2
204
SPMCLK
205
206
SPLRCK
207
208
209
210
TE
L 13942296513
211
212
ASDATA3
213
DVDD18
214
ASDATA4
215
MC_DATA
216
217
APLLVDD3
218
APLLCAP
219
APLLVSS
220
ADACVSS2
221
ADACVSS1
222
ARF (SW)
223
ARS/SDATA3
224
AR/SDATA1
225
226
AL/SDATA2
227
ALS/SDATA 0
228
ALF/(CTR)
229
ADACVDD1
230
ADACVDD2
231
RFGND18
www
232
RFVDD18
233
234
.
235
236
237
http://www.xiaoyu163.com
Name
I/O
O
Video data output bit 0 Compensation capacitor
FS
O
Full scale adjustment
VREF
O
Bandgap reference voltage
-
3.3V power pin for VIDEO DAC circuitry
Audio serial data 0 (Front-Left/Front-Right) DSD data left channel Trap value in power-
I/O
on reset
I/O
GPIO
I/O
GPIO
GPIO_4
I/O
GPIO
GPIO_3
I/O
GPIO
I/O
TP155
I/O
TP152
I/O
KEYSCAN C6
SPDATA
I/O
KEYSCAN C7
I/O
ADAC MC
SPBCK
I/O
TP165
DVDD3
-
3.3V power pin for internal
Audio left/right channel clock Trap value in power-on reset: I) 1 : use external 373 II)
ALRCK
I/O
0: use internal 373
ABCK
O
Audio bit clock Phase de-modulation
ACLK
O
Audio DAC master clock
I/O
TP152
-
1.8V power pin for internal
I/O
TP151
I/O
Inout PD SMT
SPDIF
O
SPDIF output
-
3.3V Power pin for audio clock circuitry
O
APLL External
-
Ground pin for audio clock circuitry
-
Ground pin for AUDIO DAC circuitry
-
Ground pin for AUDIO DAC circuitry
O
AUDIO DAC Sub-woofer channel output While internal AUDIO DAC not used: GPIO
O
TP149
O
AUDIO DAC Right channel output While internal AUDIO DAC not used: a. SDATA1
AVCM
O
AUDIO DAC reference voltage
AUDIO DAC Left Surround channel output While internal AUDIO DAC not used:
O
a. SDATA2
O
TP148
O
TP147
-
3.3V power pin for AUDIO DAC circuitry
-
3.3V power pin for AUDIO DAC circuitry
-
Analog ground
-
Analog power 1.8V
x
ao
XTALO
O
27M crystal out
y
XTALI
I
27M crystal in
i
JITFO
O
The output terminal of RF jitter meter.
JITFN
I
The input terminal of RF jitter meter.
PLLVSS
-
Ground pin for data PLL and related analog circuitry.
http://www.xiaoyu163.com
8
Q Q
3
6 7
1 3
u163
.
7-5
2 9
9 4
2 8
Description
1 5
0 5
8
2 9
9 4
m
co
9 9
2 8
9 9

Hide quick links:

Advertisement

Table of Contents
loading

Table of Contents