Sharp LC-37XD10 Service Manual page 76

LC-37XD10E/RU
AA4
AA2
Y4
AB2
AB3
AC2
AD2
AE2
AF4
AF5
A16
A13
A11
A12
AF6
AD14
AE14
AC14
AF16
AF14
AE13
P1
P3
C23
C22
B23
D19
B18,C18,D18,C19,C20,D20,
C21,D21
P23
M24
M26
N26
K26,J25,H24,J24,L26,L25,L
24,M23
L3
K1
J1
K3
K2
N4
J2
L2
L1, N3
N1
N2
P4
VDDAADAC -
VSSAADAC -
VDDASADAC -
VCCAADAC -
GNDAADAC -
VCCASADAC -
IREF I
VBGFIL I
LPCLKIN I
LPCLKOSC I/O
NO32XTAL1 I
CLK27MA I
CLKSPEEDSEL I
AUXCLKOUT O
notRESET I
notWDOGRSTOUT O
TDI I
TMS I
TCK I
notTRST I
TDO O
DCUTRIGGERIN I
DCUTRIGGEROUT O
TSIN2LBYTECLK I/O
TSIN2LBYTECLKVA I/O
LID
TSIN2LERROR I/O
TSIN2LPACKETCLK I/O
TSIN2LDATA[7:0] I/O
TSIN1BYTECLK I
TSIN1BYTECLKVALI I
D
TSIN1ERROR I
TSIN1PACKETCLK I
TSIN1DATA[7:0] I
notEMIRAS or O
notCI_IORD1
not_EMICAS or O
not_CI_IOW1
notEMICSA O
notEMICSB O
notEMICSC O
notEMICSD O
notEMICSE O
notEMICSF O
notEMIBE[1:0] O
notEMIOE or O
not_CI_OE
notEMILBA or O
notCI_Wea
EMIWAITnot- I
TREADY
3.3 V power for audio DAC
Ground for audio DAC command switches
3.3 V power for audio DAC substrate
3.3 V power for audio DAC command switches
Ground for audio DAC
3.3 V power for audio DAC command switches
substrate
Audio DAC output reference current
Audio DAC filtered output reference voltage
Low power clock input (1.8 V tolerant)
Low power clock oscillator (1.8 V tolerant)
Select for 32 kHz clock source
0: XTAL, 1: Internal divider
Selectable input clock to PLL or for x1 mode (5 V tolerant)
PLL speed select (5 V tolerant)
Auxiliary clock for general use (5 V tolerant)
System reset (1.8 V tolerant)
Internal watchdog timer reset (5 V tolerant)
Boundary scan test data input (5 V tolerant)
Boundary scan test mode select (5 V tolerant)
Boundary scan test clock (5 V tolerant)
Boundary scan test logic reset (5 V tolerant)
Boundary scan test data output (5 V tolerant)
External trigger input to DCU (5 V tolerant)
Signal to trigger external debug circuitry (5 V tolerant)
Transport stream bit clock (5 V tolerant)
Transport stream bit clock valid edge (5 V tolerant)
Transport stream packet error (5 V tolerant)
Transport stream packet strobe (5 V tolerant)
Transport stream data (5 V tolerant)
Transport stream bit/byte clock (5 V tolerant)
Transport stream bit/byte clock valid edge (5 V tolerant)
Transport stream packet error (5 V tolerant)
Transport stream packet strobe (5 V tolerant)
Transport stream data in (5 V tolerant)
Row address strobe for SDRAM
Column address strobe for SDRAM
Peripheral chip select A
Peripheral chip select B
Peripheral chip select C
Peripheral chip select D
Peripheral chip select E
Peripheral chip select F
External device data bus byte enable. 1 bit per byte of the data bus.
External device output enable.
Flash device load burst address.
External memory device target ready indicator (5 V tolerant)
5 – 20
VDDADC
A
GNDA-
DAC
VDDA-
DAC
VDDA
GNDA-
DAC
VDDA
VBGFIL
CLOCK
IN
CLOCK
TCK
CLK27MH
Z
SYSRE-
SET
TDI
TMS
TCK
NOT-
TRST
TDO
TRIGIN
TRIGOUT
TS2CLK
TS2VAL
TS2STRT
TS2D[7:0]
FECLK
FEVALID
FEER-
ROR
FES-
TROUT
FED[7:0]
EMIRAS
EMICAS
EMICSO
EMICS3
EMICS5
EMIBE1,
EMIRAS
EMIOE
EMILBA
CPUWAIT